Question

Design Task 2: One Second Prescalar In many systems it is desirable to have a very fast system clock to clock most of the sequential entities in the system. However, there may be other sequential entities in the same system that need to be clocked at a much slower speed. An approach that allows flexibility in generating a slower clock frequency is a frequency divider, also called a prescalar. This is basically a counter that generates a pulse every n cycles of its input clock. The output occurs as a pulse with a frequency that is 1/n of the input clock frequency. However, the output pulse has a fixed duration that is one clk period long. 4 The prescalar to be designed is named one_sec_prescalar. If its cnt_en input is asserted at a rate of 32.768 kHz it must generate an output pulse every second. So, this design divides down it input by 32768. The input pulse is one system clock in duration and output pulse is one system clock in duration. This entity must also generate an output named one_hz that is a 1Hz square wave. The entity declaration for the one second prescalar is:

entity one_sec_prescalar is port( clk : in std_logic; -- system clock

rst_n : in std_logic; -- active low synchronous reset

clr_n : in std_logic; -- synchronous clear

cnt_en : in std_logic; -- count enable

one_hz : out std_logic; -- one Hz square wave output

one_sec_tick : out std_logic -- one clock wide pulse every sec );

Answer 1

Since you need 1 Hz as output. And you have 32.768 kHz as input. So, you need divide the input by 32768 which is 8000 in Hex to input pulse. so we set prescale value which will count till 32768 pulse and after it increase the pulse of output signal.


library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;

entity one_sec_prescalar is 
port (
    clk_32768hz : in  std_logic;
    rst_n       : in  std_logic;
    one_hz   : out std_logic);
end one_sec_prescalar;

architecture Behavioral of one_sec_prescalar is

  signal prescaler : unsigned(15 downto 0);
  signal clk_1Hz_i : std_logic;
begin

  gen_clk : process (clk_32768hz, rst)
  begin  -- process gen_clk
    if rst = '1' then
      clk_2Hz_i   <= '0';
      prescaler   <= (others => '0');
    elsif rising_edge(clk_50Mhz) then   -- rising clock edge
      if prescaler = X"8000" then     -- 32768 in hex
        prescaler   <= (others => '0');
        clk_1Hz_i   <= not clk_1Hz_i;
      else
        prescaler <= prescaler + "1";
      end if;
    end if;
  end process gen_clk;

clk_1Hz <= clk_1Hz_i;

end Behavioral;