A three-phase asynchronous motor with 380 Δ / 660 λ, 35 Kw, 1400 rpm label on the label will be started in 380 volt network.
Draw the control and power circuit according to the requests below.
A) The motor will be turned right and left
B) Motor will be protected against overcurrent and two phases
C) The green lamp will light when the engine is turning to the right and the blue lamp will be turning when turning to the left.

What is flashover and arcing? How do they happen and why?

 How can we keep the terminal voltage equals to constant independently from load change?

Write a Matlab code for PSK modulation of Polar signal full widht rectangular pulses and data rate 1 mbit/s also find PSD of psk and estimate Bandwidth

A movie theater is planning to offer the possibility to book the seats either online or at the kiosk of the theater. Design the booking application for the theater taking in account the following consideration:

- The theater has 100 seats only.

- More than one user may be trying to book the same seat at the same time.

- Any seat can be booked by only one user.

- A seat can be available for the kiosk agent and the online user at the same time but can be booked by only one of them.

- If the client did not book a seat online or changed his/her mind at the kiosk, the seat must be available again for booking.

Use the process synchronization techniques. You are allowed to use variables as much as you need in the design.

The code does not have to be complicated or detailed. Thanks for the help!

The parameters of a 3-phase, 4-pole, 50 Hz, Y-connected, wound-rotor induction motor are listed below. These are the default values of the “Asynchronous Machine” model in MATLAB Simulink. r1=0.5968 ?; r2=0.6258 ?; L1=0.0003495 H; L2=0.005473 H; Lm=0.0354 H; Stator line voltage = 400 V rms. The motor for rotor speeds nm= 0 to 1500 rpm.

X1= 0.1097 ohm, X2= 1.719 ohm , Xm= 11.12 ohm, RTH = 0.5853 , XTH = 0.1395 and VTH = 230.82 V.

Suppose the motor is to rotate a fan for which the load torque is proportional to cube of the speed: ?m = (1.3×10^ -5 )*?m^3 where ?m is the fan speed in rad/s. Then use MATLAB to plot the torque-speed characteristic of the fan as the motor torque-speed characteristic. What would be the motor speed and torque?

*************** Please do not copy and paste from other answered questions on Chegg, *******************

Overview

In this assignment you are required to implement binary code comparator using Xilinx that it is compatible with the MXK Seven Segment Displays. You will draw your digital logic circuit using Xilinx and then simulate it to verify the functionality of your design.

Software Requirements

? Xilinx ISE 10.1 or higher

Specifications

Binary Code Comparator

The binary code comparator is to be implemented and made compatible with the seven 7-segment displays of the board. Represent the first five digits of your student number into binary. If a given decimal digit is odd, then the binary equivalent will be 1, otherwise it will be 0. For example, the student (decimal) number 99805234 will produce 11001. The user is to enter a 5-bit binary sequence one bit at a time. The five bits will be displayed on five of the seven segment displays. If the five entered bits equal to the stored binary code, then ‘E’ is to be displayed on the sixths seven- segment display. However, if the five entered bits do not equal the binary code, then ‘n’ is to bedisplayed. Note that you do not have to display bits as they are received in accumulating manner (as shown in the figure below), rather, you can display all five bits and the comparator outcome (‘E’ or ‘n’) when the fifth bit is received. All six seven-segment displays are to stay on for five seconds, then they will be erased. Once the displays are erased, the circuit will be ready for receiving a new set of five input bits.

- Reset: if pressed, the circuit will return to the initial state and all seven segment displays are to be erased.

- Input (could be received from a dipswitch in your MXK): to specify the binary input (1 or 0).

- Trigger (could be received from a pushbutton in your MXK): to allow the input to be received by the circuit.

- Clock: to alternate between the 7-segment displays (expected to be around 1000 Hz).

There are two sets of outputs, which are:

- d1, d2, ..., d7 (anodes to switch between the seven 7-segment displays)

4)Design a band-pass filter with a passband from 500 Hz to 2000 Hz using “butter” routine of MATLAB. Assume a sampling frequency of 8KHz. Let the filter order be M=4. Plot the magnitude response and provide the filter coefficients and the transfer function

2. (CLO_1): (Cognitive Level C2, i.e., Comprehension) (PLO_1, i.e., Engineering Knowledge) Explain the following devices with the help of the construction diagram and device operation
   1. n-channel JFET
   2. n-channel Depletion MOSFET III-     n-channel Depletion MESFET

sir I want to make discrete time Fourier series on GUI MATLAB can any one tell me step by step procedure or coding for Discrete time Fourier series on GUI? pleaseeeee

Create a state meachine that encrypts an incoming digital bitstream using a D-flip-flop and a Mealy Meachine. The device have to meet these requirments:

A. The output of the encryption device matches the input bitstream until a certain set of bits is detected (such as 110). After this detection, the output is the complemented version of the input.

B. When a second bitstream 010 is detected, the output reverts to simply matching the input stream again. Please make both bitstreams that cause the switching action to be at least 3 bits in length.

Please include the following for the above questions:

1. A state graph for the machine.

2. The state tables, truth tables, and K-maps that you used to design the machine.

3. Give the example bitstream output demonstrating the machine in operation. Example bitstream: 0111010001110101

Approximately how many ft (m) of cable are required to connect the oven in the residence?

Can someone create a Test bench for this 4 Bit USR code so that it can shift left, shift right and Load. This is in VHDL. Please type out the code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Uni_reg is
port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right
Da,Db,Dc : in std_logic; --inputs for load
Qa,Qb,Qc : out std_logic); --out puts from the flipflops
end Uni_reg;

architecture Structural of Uni_reg is

signal lr1,lr2,sp1,sp2,R1,R2,R3 : std_logic;
signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic;
signal c1,c2,c3 : std_logic;
signal Qas,Qbs,Qcs : std_logic;

component andgate
port(a,b,c : in std_logic; z : out std_logic);
end component;

component orgate
port(a,b,c : in std_logic; z : out std_logic);
end component;

component notgate
port(a: in std_logic; z : out std_logic);
end component;

component Dflipflop
port(D,clk: in std_logic; Q: out std_logic);
end component;

begin

NOTGATE1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT
NOTGATE2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT
NOTGATE3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL
NOTGATE4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL

ANDGATE1: andgate port map (shR,sp2,lr2,R1); --for right shift of 1st bit
ANDGATE2: andgate port map (sp2,lr1,Qbs,L1); --for left shift of 1st bit
ANDGATE3: andgate port map (lr2,sp1,Da,LOAD1);--for load of 1st bit
ANDGATE4: andgate port map (Qas,sp2,lr2,R2); --for right shift of 2nd bit
ANDGATE5: andgate port map (sp2,lr1,Qcs,L2); --for left shift of 2nd bit
ANDGATE6: andgate port map (lr2,sp1,Db,LOAD2);--for load of 2nd bit
ANDGATE7: andgate port map (Qbs,sp2,lr2,R3); --for right 3rd bit
ANDGATE8: andgate port map (sp2,lr1,shL,L3); --for left 3rd bit
ANDGATE9: andgate port map (lr2,sp1,Dc,LOad3);--for loading 3rd bit

ORGATE1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop
ORGATE2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop
ORGATE3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop

FLIPFLOP1: Dflipflop port map (c1,clk,Qas);
FLIPFLOP2: Dflipflop port map (c2,clk,Qbs);
FLIPFLOP3: Dflipflop port map (c3,clk,Qcs);

process(clk,clear)
begin
if clear ='1' then
c1<='0';
elsif (clk'event and clk = '1') then
c1<=c1;
Qa <= c1;
end if;
end process;

process(clk,clear)
begin
if clear ='1' then
Qbs<='0';
elsif (clk'event and clk = '1') then
Qbs<= Qbs;
Qb <= Qbs;
end if;
end process;

process(clk,clear)
begin
if clear ='1' then
Qcs<='0';
elsif (clk'event and clk = '1') then
Qcs<=Qcs;
Qc <= Qcs;
end if;
end process;

end Structural;

For Bi-convex lens, Bi-concave lens Concave Mirror and Concave mirror :

1 ) By looking at the lens and mirrors in person, comment on the orientation and location of the images you see?

2 )How could these types of lens be used for lighting purposes?