Compute the ?p(kg • m/s) for the red chart and the blue chart and the ?psys.

Using the programing language of Verilog I attempted to make a counter to count from 0 to 9 then loop back to 0 using the internal clock of the FPGA cyclone IV from altera. the code is posted at the bottom

I get the following errors

Error (10663): Verilog HDL Port Connection error at Encryption.v(9): output or inout port "clk" must be connected to a structural net expression

Error (10285): Verilog HDL Module Instantiation error at Encryption.v(9): instance "" specifies 3 actual port connections but module "clockgen" only expects 2

Error (12153): Can't elaborate top-level user hierarchy

Can someone help me debug this code so it can count up to 9

module Encryption(SW, CLOCK_50, OUT, HEX0);

input[1:0]SW;

input CLOCK_50;

output reg[6:0] HEX0;

output [3:0]OUT;

wire S1, S2, S3;

clockgen(CLOCK_50, 25000000,clk);

Tflipflop(SW[0], clk, SW[1], OUT[0]);

and(S1, clk, SW[0], OUT[0]);

Tflipflop(S1, clk, SW[1], OUT[1]);

and(S2, S1, OUT[1]);

Tflipflop(S2, clk, SW[1], OUT[2]);

and (S3, S2, OUT[2]);

Tflipflop(S3, clk, SW[1], OUT[3]);

always

begin

case(OUT)

4'b0000: HEX0 = 7'b1000000;

4'b0001: HEX0 = 7'b1111001;

4'b0010: HEX0 = 7'b0100100;

4'b0011: HEX0 = 7'b0110000;

4'b0100: HEX0 = 7'b0011001;

4'b0101: HEX0 = 7'b0010010;

4'b0110: HEX0 = 7'b0000010;

4'b0111: HEX0 = 7'b1111000;

4'b1000: HEX0 = 7'b0100000;

4'b1001: HEX0 = 7'b0010000;

4'b1010: HEX0 = 7'b0001000;

4'b1011: HEX0 = 7'b0000011;

4'b1100: HEX0 = 7'b1000110;

4'b1101: HEX0 = 7'b0100001;

4'b1110: HEX0 = 7'b0000110;

4'b1111: HEX0 = 7'b1001110;

endcase

end

endmodule

module Tflipflop(En, Clk, Clear, Q);

output Q;

input En, Clk, Clear;

reg Q;

always @(posedge Clk)

if (Clear == 0)

begin

Q = 1'b0;

end

else

begin

Q = En^Q;

end

endmodule

module clockgen(clk_in, clk_out);

input clk_in;

output[3:0] clk_out;// count up to 9 length must be 4 so [3:0]

reg[3:0] counter = 0; //temp variable

always@(posedge clk_in)

begin

if(counter< 9)

counter<=counter+1;//manupulate temp variable

else

counter = 0;

end

assign clk_out = counter;//assigning temp variable value(counter in always block) to the output variable

endmodule

what is the voltage output specification of the charging system when a load is placed on the system?

DTMF Home Automation System

This project is about controlling of home appliances using DTMF (Dual Tone Multi Frequency) technology. These appliances includes lights, fans, central heating, etc. A control unit will be required to encode the 4bit binary code from the DTMF decoder to link with 16 appliances or operations. However anyone can control your appliances if they know the cell number of the phone connected to the module. Furthermore, the number of appliances is limited to 16, which is the number of DTMF tones. These problems can be solved by using a controller at both transmit and receive end, and introduce a digital code. Now it will be possible to use more than one tone per command. For example, using 2 tones will give 16x16 =256 commands. A duplex operation can now be possible.

I need help Designing the DTMF Home Automation System using an Arduino.

I need the source code and circuit

Set up and demonstrate the operation of the DTMF controlled automation system, using a designed control unit.

what are the ingredients to design a security system using Microcontroller MSP 430? and what is the proper flowchart for this system?

Sketch the waveform of the letter g when it is transmitted via the USART interface, using the format of 1 start bit, 8 data bits and 1 stop bit

Sketch the waveform of the letter g when it is transmitted via the USART interface, using the format of 1 start bit, 8 data bits and 1 stop bit

Calculate several samples of the unit impulse and impulse responses of y(n) = -0.75 y(n–1) + x(n) – 0.3 x(n–1) – 0.4 x(n-2).

Re-write the equation in standard form and then indicate the name of each coefficient (a₁, etc.). Use the filter() function in MATLAB to check your results to 1 and 2.

I blurred a grayscale image using a 5x5 average filter and then I am supposed to deblur using an Inverse filter using Constrained Division. Is there a better way to do this?

The error that pops up is this:

 Error using  ./ 
 Complex integer arithmetic is not supported.

 Error in test2 (line 12)
 fbw = fftshift(fft2(blur))./bw;

When I blur the image using a butterworth filter it works just fine yet when I blur using the average filter my code won't work. Below is my attempt:

 clear
 I = imread('buffalo.png');
 H = fspecial('average',[5 5]) ;
 blurred=imfilter(I,H);
 blur=im2uint8(mat2gray((blurred)));
 imshow(blur)

 d = 0.01;           
 bw = blurred;        
 bw(find(bw<d)) = 1; 
 fbw = fftshift(fft2(blur))./bw; 
 ba = abs(ifft2(fbw)); 
 unb01 = im2uint8(mat2gray(ba));

Make a table that summarizes results over the last four years (2013-2017 only) in understanding degradation in amorphous silicon solar cells. The table should have two columns: (1) Brief description of the main results in the paper, and (2) Reference for the paper

Create a simulink model of the nonlinear equation (1) and obtain a plot from 0 to 3 seconds of the

pendulum problem. Be sure to include a scope box so the displacement plot can be viewed.

d2q/dt2 + (g/L)*sinq = 0

q = angle of displacement of the pendulum [rad]

g = gravitational constant 9.81 [m/sec2 ]

L = pendulum length [m]

      The sinq term introduces the nonlinearity. This makes the solution difficult. To simplify the problem,       equation is linearized by using the approximation that sin q = q. This is a valid approximation for small angles of q only. Run

and create a scope plot for displacement vs time for approximately 5 cycles of a 0.5 m long pendulum that has a starting angular displacement of 10 degrees and an initial angular velocity of – 10 m/sec. Note use the linearized equation.

How would you design a cache coherence with only MS, not MSI. How do you manage the new protocol?

Draw the new MS protocol. For each state, show all the relevant transitions.

In the new MSI protocol, when does a memory read occur? Specify the bus transaction, the requestor's start and end states, and the states of the other caches if relevant.

In the new MSI protocol, when does a memory write occur? Specify the bus transaction and the requestor's start and end states. Specify any other scenario where a memory write occurs.

Consider the following discrete memoryless channel: Y = X + Z, where Pr{Z = 0} = Pr{Z = a} = 1/2 and the alphabet for x is {0, 1}. Assume that Z is independent of X.

a) Find the capacity of the channel in terms of a.

b) Explain how capacity is affected by a in terms of signal-to-noise ratio (SNR).

Create a counter that continuously counts odd numbers backwards (i.e from ‘F’ to ‘0’) and display it on 7-sd by using the Verilog code.

On this part, you are required to use the clock from the FPGA board. However, the clock frequency is 100 MHz, and it is too fast to be used (10 ?s). Thus, we need to derive a slower clock with a speed of almost 1 s, which the frequency of it is 1 Hz. This process is called clock division.

MY FPGA is BASYS 3 and program must be written in verilog. Could you please help me? At least write the design code.

If you help me, I will be the happiest person in the world.