Design a “disk spinning” animation circuit for a CD player. The input to the circuit will be a 3-bit binary number A1, A2, A3 provided by 3-bit up counter. The circuit for 3-bit counter has already been provided in CCT file on Google Classroom, so there is no need to design the up counter yourself.
The animation will appear on the top four lights of the LED display of Figure, i.e., on X1, X2, X7, and X6, going clockwise as shown in Figure 1.
Figure 1 Seven Segment Indicator
The animation should consist of a blank spot on a disk spinning around once, beginning with X1. Then, the entire disk should blink on and off twice. The pattern is shown in figure 2.
Figure 2 Disk Spinning Pattern
You have to design a circuit that must use two 2x1 multiplexers, and two 4x1 multiplexers in the design. You may also use logic gate(s) in the design.
(a) Draw the truth table for the circuit below. The truth table must cover all the possible cases. Stick to the notations use in the question.

(b) Drive the input equations for the multiplexers.   

(c) Implement the same circuit on LogicWorks. The output of the circuit must be shown through 7Seg Disp component in the LogicWorks. There is no restriction on the selection of 2x1 mux and 4x1 mux variants available in the LogicWorks. You have to connect the up-counter circuit already provided to you with your designed circuit

The following logic function is given as a sum of minterms F(W,X,Y,Z) = ∑W,X,Y,Z(7,8,10,11,13) + D(5, 9, 15). (25 points)
a) Draw the K-Map and find the minimal sum-of-products expression for this function.

b) Draw the circuit implementing this expression

c) Give all input pair or pairs where transition between them would create a timing hazard

d) Draw the timing diagram showing the glitch corresponding to the pair or one of the pairs. Assume ALL gate delays are equal

e) Suppose the delay of each gate was measured to be 1 ns, with the exception of one AND gate of your choosing. Assume you have the ability to increase the delay of ONE AND gate past 1 ns. Which gate would you choose and what would be the new delay value that removes the glitch? Show the new waveform.

f) Provide the expression of an equivalent logic function in which the timing hazard is eliminated for any gate delay condition. No need to show new waveforms.

g) Suppose that cost, area, and power consumption are of zero concern for this design (you have infinite resources). Would you rather implement the solution from part (e) or part (f)? Explain your choice.

Study the below case and answer the following questions:

Rania is an Electrical Quality Assurance Engineer at a large electrical company. she is responsible for the final testing of her company’s transformers and she is part of a team which decides when new the products will be shipped to distributors for sale.

Rania’s company has a contract with another company which produces wires inside the transformers Rania’s company make. The transformers need to be shipped for the costumer by the end of the month, meaning Rania has a limited timeframe to conduct her Quality Control test for the wires.

Due to such a short notice, the Quality and Assurance department cannot perform all the tests required on the wires to ensure they are defect free. Rania suspects that there is malfunction in some of the wires and cannot send her confirmation test until she assures that all issues have been fixed or replaced. However, if she doesn't, her company's competitor will take the contract.

Questions

a. Would it be ethical for Rania to send her confirmation test under these circumstances?

(I) It is not ethical for Rania, to send her confirmation test s as it jeopardizes the public safety.

(II) It is ethical for Rania, to send her confirmation test

b. Refer to the NSPE Code of Ethics for Engineers to explain which ethical code does Rania will consider to justify her action?

A radio receiver operating at 477MHz with minimum sensitivity of -85dBm is connected to an antenna with gain +12dBi using a feeder cable with loss of -3dB.The transmitter is 40Km away and uses a parabolic antenna with gain of +23dBi. The transmitter feeds the antenna through a coaxial cable with -6dB loss. What is the minimum transmitter power required for reliable operation of the link assuming a fade margin of 10dB?

develop an information brochure, infographic or webpage that could be found on a website promoting the benefits of renewable energy. Your information brochure/infographic/webpage should include:

• An overview of the electrochemical object.
• The information you learned through researching your inquiry questions.
• The implication of this electrochemical object for society, health and safety and the environment.

What do you mean by convolution operation? Explain why it is a complex operation? Show the difference between linear and circular convolution, with an example.

In designing static CMOS Logic circuits a principle of pull –up networks and pulldown networks is applied . Explain in your own understanding how this principle
works.

b) Atom is a particle which can be broken into proton ,neutron and `electron . With
diagrams, explain how electrons are placed on shells and sub shells around the
nucleus?

Design a common emitter transistor so that it will operate in the linear region with a max swing on the output. Use a voltage divider configuration with a collector current of Ic = 2mA and a supply voltage of 12 V.Choose Ve =10% of Vcc.

Draw the circuit diagram and calculate all the resistor values

Find out the amplitude ,frequency and phase displacement for given QPSK signal

(a) 100 cos(25t+π/4).

(b) 33.33 sin (350t+ 3π/4) .

A 325 V sinusoidal voltage generator at 50 Hz supplies a load modelled by a
35  resistance in series with a 95.5 mH inductor. The loss of the transmission line between
the generator and the load is modelled by a series resistance of 5 . Calculate the average,
reactive and apparent power a) consumed by the generator, b) consumed by the load.
Determine the power factor at which the load is operating.

Please outline the method clearly.

Answers should be: 633.75 var of reactive power. 845 W of average power

Write the equation that describes the behavior of excess charge carriers in a p-type semiconductor under low-level injection.

Analyze the ADC circuit to obtain the graphs for the output of the comparator and DAC (ladder network) for a 4-bit ADC if the reference voltage is 11V and the input voltage is 7.5V. Also find the quantization error. Also draw the circuit

with a voltage range of 0.874 and -0.855 how can i design a inverting amplifier using standard resistors to produce a voltage output range of -10 to 10 volts?