Question

In: Electrical Engineering

The following logic function is given as a sum of minterms F(W,X,Y,Z) = ∑W,X,Y,Z(7,8,10,11,13) + D(5,...

The following logic function is given as a sum of minterms F(W,X,Y,Z) = ∑W,X,Y,Z(7,8,10,11,13) + D(5, 9, 15). (25 points)
a) Draw the K-Map and find the minimal sum-of-products expression for this function.

b) Draw the circuit implementing this expression

c) Give all input pair or pairs where transition between them would create a timing hazard

d) Draw the timing diagram showing the glitch corresponding to the pair or one of the pairs. Assume ALL gate delays are equal

e) Suppose the delay of each gate was measured to be 1 ns, with the exception of one AND gate of your choosing. Assume you have the ability to increase the delay of ONE AND gate past 1 ns. Which gate would you choose and what would be the new delay value that removes the glitch? Show the new waveform.

f) Provide the expression of an equivalent logic function in which the timing hazard is eliminated for any gate delay condition. No need to show new waveforms.

g) Suppose that cost, area, and power consumption are of zero concern for this design (you have infinite resources). Would you rather implement the solution from part (e) or part (f)? Explain your choice.

Solutions

Expert Solution

Given. F(W,X,Y,Z) = ∑W,X,Y,Z(7,8,10,11,13) + D(5, 9, 15)

a) The truth table for the given function is,

The K map for F is,

The expression obtained from Kmap is,

b) The circuit implemented with the above expression is given below.

c) The input pair where transition between them would create a timing hazard is for the inputs W and X which are fed to AND gate, where W is directly given to its input and X is fed through an inverter.

d) Consider the circuit given below with some intermediate signal labels.

Below is the timing diagram when there is a transistion in the inputs, W and X.

Assuming all gate delays are equal and as 1 unit in the timing diagram.

When W=0 and X=0 ,ie. X' =1 resulting in F1=0 after 1 unit delay. When W and X changes to 1, X' becomes 1 after a 0 unit delay. Before X' becomes 0 after the change in X to 1, for a 1 unit period, the value of F1=1 for the next 1 unit as W=1 and X' =1. This is a glitch.The F1 value will become correct only after X'=0,ie. value after the glitch in F1.


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