Three balanced three-phase loads are connected in parallel. Load 1 is Y-connected with an impedance of 420+300i Ω/ϕ ; load 2 is Δ-connected with an impedance of 2400-1780i Ω/ϕ ; and load 3 is 170.1+2201i kVA . The loads are fed from a distribution line with an impedance of 2+17i Ω/ϕ . The magnitude of the line-to-neutral voltage at the load end of the line is 23√3 kV.

Part A: Calculate the total complex power at the sending end of the line.

Part B: What percentage of average power at the sending end of the line is delivered to the loads.

Hello, i Have an OPAMP of 66dB ,how using negative feedback we can reduce the closed loop gain to 16dB

Thanks

1. Design and simulate a first order low pass filter so that it has a cutoff frequency of 2 kHz and a passband gain of 1.
2. please use online multisim

Explain in detail how Zener diodes can be used as a protection circuit for the instrumentation used in a biopotential measurement.

Explain why the direction of the rotor field is reversed when two phases of power are connected upside down.

1. (10 pts) A mobile receiver communicates with the transmitter at an operating frequency of 550 MHz at a distance of 3 km. Calculate the path loss in the system.

2. (15 pts) Assume that two antennas are half-wave dipoles and each has a gain of 3 dB. If the transmitted power is 1 W and the two antennas are separated by a distance of 10 km, what is the received power? Assume that the frequency is 100 MHz.

3. (10 pts) Show that doubling the transmission frequency or doubling the distance between transmitting antenna and receiving antenna reduces the received power by 6 dB.

Problem 2. Derive 1-D wave equation for Hy(z,t), and prove that Hy given in equation 9.32 in the textbook is a solution of the 1-D wave equation.

The 500 KVA, 69kV/11kV, 60 Hz transformer has total resistance Rp of 100 Ω and total leakage reactance of Xp of 600 Ω. Calculate

1. The per unit impedance of the transformer in percent (just magnitude)

2. The voltage regulation of the transformer when it delivers 200 KVA with a lagging power

   factor of 90% while the secondary voltage is fixed at 11 kV.

3. The actual primary voltage V1.

4. The actual line current I1.

Explain what is meant by the “driven right leg” circuit. What function does it serve? How is it modeled (include a figure) in a circuit schematic?

A four-pole dc machine has a simplex-wave winding of 250 turns. The flux per pole is 0.7 T. The armature radius is 15 cm and effective conductor length is 20 cm. The pole covers 80 % of the armature periphery. The machine rotates at 1000 rpm.
1. Determine the machine constant (see sec. 4.2.4 of the text book).

2. Determine the generated voltage.

3. Determine the kW rating if the rated current through a single-turn is 120 A.

4. The machine developed torque

Using Multisim, design a 2-bit, synchronous binary counter and verify that it counts in the right sequence, Can count up or down and use any FF you desire; 4 screen shots in total: 1 for each input combination

Q7.1    The normalized passband edge angular frequency Wp is - 0.2
   The normalized stopband edge angular frequency Ws is - 0.4
   The desired passband ripple Rp is - 0.5 dB
   The desired stopband ripple Rs is - 40 dB

In Matlab:

Q7.X1 Design a Butterworth lowpass filter satisfying the specifications in Q7.1. Plot the magnitude and phase responses. Also include magnified plots of passband and stopband showing how well the filter satisfies the design specifications.

Write a literature review from any article concerning the regenerative braking system for electric vehicles  make sure your literature review contains the f.f

• Include a brief description with appropriate illustrations
• Discuss the concepts, approach, methods, analysis, and issues.
• Identify the limitations
• Suggest improvements.

(i) Consider a CMOS inverter supplied at V_DD= 5V with transistor parameters of K_N=K_P=50µA/V² and V_TN=-V_TP=1V. Then consider another CMOS inverter supplied at V_DD= 10V with the same transistor parameters. Draw the VTC of both inverters showing all regions of operation and the middle voltage VM. Verify your results using PSpice.

            (ii) Draw the square root of the CMOS inverter current versus the input voltage for the two CMOS inverters in given in part (i) biased at either V_DD=5 V or V_DD=10 V. Determine the peak current of the CMOS inverter at V_DD=5 V & V_DD=10 V. Verify your results using PSpice.

(iii) Consider NMOS inverter supplied at V_DD= 5V with transistor parameters of K_Driver=10 K_Load=100µA/V² and V_T =0.7V. Calculate the power dissipated for the following input conditions: Vin= 0.25 V and Vin=4.3 V.

(iv) If two NOR gates based on the CMOS inverter given in part (i) which supplied at V_DD= 5V are connected to realize an SR Flip Flop. Sketch the NOR gate and sketch the complete circuit of the SR Flip Flop indicating the S and R inputs a well as the Q output. What are the logic”0” and logic “1” levels of this Flip Flop?

(v) If two NOR gates based on the NMOS inverter given in part (iii) are connected to realize an SR Flip Flop. Sketch the NOR gate and sketch the complete circuit of the SR Flip Flop indicating the S and R inputs a well as the Q output. What are the logic”0” and logic “1” levels of this Flip Flop?