Question

In: Computer Science

If A is a 32-bit address, typically an instruction sequence such as: lui x19, A_upper addi...

If A is a 32-bit address, typically an instruction sequence such as: lui x19, A_upper addi x19, x19, A_lower can be used to load the word at A into a register (in this case x19).

a) How many bits of A are in A_upper?

b) If the MSB of A_upper is 1, what would be the value of the leftmost 32-bits of register x19. Provide your answer in decimal.

c) After the lui instruction, the rightmost 12-bits of x19 would be filled with all 1’s. True or False?

d) If the bit 11 (12th bit) of A is 1, how should A_upper be changed? Choose (X) one of the following (A_upper = A_upper + 1) / (A_upper = A_upper - 1) /(None)

e) What other instruction can be used instead of addi?

Solutions

Expert Solution

Greetings!!

Generally lui and addi instructions are used as a combination of instructions which can be used to load a 32 immediate value into a register and are used instead of the instruction li. For example, if register x19 needs to be filled with immediate value 0x81223344, the instruction li x19,0x81223344 is used. Otherwise lui and addi pair of instructions can be used as follows:

lui x19,0xFFF81223 #which will load the upper register with 0x81223000 and lower 12 bits with 000

8 1 2 2 3 0 0 0

addi x19,x19,344 #which appends the value 334 so that the register contains 0x81223344 at the end

8 1 2 2 3 3 4 4

a) A_upper is the Most significant 20 bits of A.

ie 0x81223344[Please note that each digit consists of 4 bit binary and hence 20 bits ie 81223 is 1000 0001 0010 0010 0011]

b) Here A is 0x81223344 and has a 1 at its MSB,the register will contain 0x81223000 after the instruction lui which represents 2166501376 in decimal

c) False. The rightmost 12 bits are filled with 0s after executing the lui instruction.

d) None

e) Instead of addi instruction ori instruction can be used.

Hope this helps


Related Solutions

For a direct mapped cache design with 32 bit address, the following bits of the address...
For a direct mapped cache design with 32 bit address, the following bits of the address are used to access the cache Tag Index Offset 31 - 8 7 - 4 3 - 0 What is the cache block size (in words)? How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Address 0...
.text .globl main main:       lui $8, _______ # the address of pairs (SPIM:0x1000; Mars:0x1001)...
.text .globl main main:       lui $8, _______ # the address of pairs (SPIM:0x1000; Mars:0x1001)    lw $9, 0(_____) # get the number of pairs (6) and store in $9    ori $10, $0, 0 # use $10 to store the height sum    ori $11, $0, 0 # use $11 to store the weight sum    ori $12, $0, 0 # use $12 to count    ori $13, $0, 0 # use $13 to store temp values; addiu...
perfrome bit destuffing for the following sequence: 11101111101111100111110
perfrome bit destuffing for the following sequence: 11101111101111100111110
Design a 32 bit after using a single 4 bit using verilog code
Design a 32 bit after using a single 4 bit using verilog code
Assume that you had just received the bit sequence "10000011". Given the first bit is a...
Assume that you had just received the bit sequence "10000011". Given the first bit is a parity bit, which parity system would indicate that there has been a 1 bit transmission error? Justify your answer. Enter your answer below.
Of all bit sequences of length 8, an 8-bit sequence is selected at random. Assuming that...
Of all bit sequences of length 8, an 8-bit sequence is selected at random. Assuming that the probability of a bit being 0 is equal to that being 1, determine the probability that the selected bit sequence starts with a 1 or ends with the two bits 00.
Write an instruction sequence to configure the A/D converter of the PIC18F452 to operate with the...
Write an instruction sequence to configure the A/D converter of the PIC18F452 to operate with the following parameters: Conversion result right justified fosc=32 MHz Highest ambient temperature may reach 600oC Use VDD and VSS as the high and low reference voltages Convert channel AN0 Enable A/D Module
Show the IEEE 32-bit representation for 2.09375 and 17.1875
Show the IEEE 32-bit representation for 2.09375 and 17.1875
Encode 32-bit INTEGER 12 in TLV format?
Encode 32-bit INTEGER 12 in TLV format?
Design a 32 bit adder using a single 4 bit adder using verilog code
Design a 32 bit adder using a single 4 bit adder using verilog code
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT