We assume a superscalar pipeline capable of fetching and decoding two instructions at a time, having...

We assume a superscalar pipeline capable of fetching and decoding two instructions at a time, having two separate functional units (e.g., one integer arithmetic and one floating-point arithmetic), and having two instances of the write-back pipeline stage. Assume the following constraints on a six-instruction code fragment:

Inst-1 is a floating point operation

Inst-2 requires two cycles to execute and depends on output of Inst-1

Inst-3 and Inst-4 conflict for the same functional unit. Inst-3 and Inst-4 are floating point operations.

Inst-5 is an Integer operation

Inst-5 and Inst-6 conflict for a functional unit.

Integer operations can be performed on integer or floating point unit whichever found available but floating point operations must require floating point unit.

Show the states of different stages of superscalar processor at different clock cycles for any instruction issue policy. Please mention the policy you use to answer the question.

Expert Solution

venereology answered 6 months ago

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