Question

1. Write the logical expression for the control signal RF_Write assuming the instruction set consists only of the instructions below. The answer should be similar to "B_Select = T3 ∙ (Load + Store + AddImm + …) + …"

• Add R3,R4,R5
• Load R5,X(R7)
• Store R6,X(R8)
• Unconditional Branch
• Conditional Branch (Branch_if_[R5]=[R6] Loop)
• Subroutine Call (Call_Register R9)

Answer 1

Answer.

Step 1

Logical expression for the Control Signal:

• Add R3, R4, R5

1. Memory address <----[PC], Read memory,
   IR <---- Memory data,
   PC <-- [PC] + 4
2. Decode instruction,
   RA <---- [R4], RB <---- [R5]
3. RZ <---- [RA] + [RB]
4. RY <-- [RZ]
5. R3 <---- [RY]

• Load R5, X(R7)

1. Memory address <---- [PC],
Read memory,
IR <---- Memory data,
PC <-- [PC] + 4

2. Decode instruction, RA <-- [R7]

3. RZ <-- [RA] + Immediate value X

4. Memory address <-- [RZ],
Read memory,
RY <---- Memory data

5. R5 <-- [RY]

Step 2

• Store R6, X(R8)

1. Memory address <-- [PC],
Read memory,
IR <---- Memory data,
PC <---- [PC] + 4

2. Decode instruction,
RA <-- [R8], RB <-- [R6]

3. RZ <-- [RA] + Immediate value X, RM <-- [RB]

4. Memory address <-- [RZ], Memory data <-- [RM],
Write memory

5. No action

• Unconditional Branch

1. Memory address <-- [PC], Read memory,
   IR <---- Memory data,
   PC <-- [PC] + 4
2. Decode instruction
3. PC <-- [PC] + Branch offset
4. No action
5. No action

• Conditional branch: Branch_if_[R5]=[R6] LOOP

1. Memory address <-- [PC],
   Read memory,
   IR <---- Memory data,
   PC <-- [PC] + 4
2. Decode instruction, RA <-- [R5], RB <-- [R6]
3. Compare [RA] to [RB],
   If [RA] = [RB], then PC <-- [PC] + Branch offset
4. No action
5. No action

• Subroutine call with indirection: Call_register R9

1. Memory address <-- [PC],
   Read memory, IR <--- Memory data,
   PC <-- [PC] + 4
2. Decode instruction, RA <-- [R9]
3. PC-Temp <-- [PC],
   PC <-- [RA]
4. RY <---- [PC-Temp]
5. Register LINK <-- [RY]

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