Question

Rising Edge Detector: The rising-edge detector is a circuit that generates a short one-clock-cycle tick when the input signal changes from 0 to 1. It is usually used to indicate the onset of a slow time-varying input signal. Moore machine state diagram for the rising-edge detector is shown in Figure 6. a. Draw the state diagram for the rising edge detector b. Adapt the Code Example 1 to implement the detector in Verilog

Answer 1

//verilog code for risimg edge detector of moore fsm

module moore_fsm

(

input clock, reset, x,

output reg z

);

//assign binary encoded codes to the states A through D

parameter

s0 = 2'b00,

s1= 2'b01,

s2= 2'b10;

  

reg [1 : 0] current_state, next_state;

//Section 1: Next state generator (NSG)

always@(*)

begin

case (current_state)

s0: if ( x == 1)

next_state = s1;

else

next_state = s0;

s1: if (x ==1)

next_state = s2;

else

next_state = s0;

s2: if (x == 1)

next_state = s2;

else

next_state = s0;

default : next_state = s0;

endcase

end

//MOORR FSM Output generator

always@(*)

begin

if (current_state == s1)

z = 1;

else

z = 0;

end

//PRESENT STATE SEQUENTIAL LOGIC

always@(posedge clock, posedge reset)

begin

if (reset == 1)

current_state <= s0;

// UPON RESET STATE IS S0

else

current_state <= next_state;

end

endmodule

// rising edge detection test bench

module moore_FSM_tb();

reg clock, reset, x;

wire z;

moore_fsm u1(clock, reset, x, z);

initial begin

$monitor("%4d: z = %b", $time, z);

clock = 0;

reset = 1;

x = 0;

#10 reset = 0;

end

always begin

#5clock = ~clock;

end

initial begin

$dumpfile("test.vcd");

$dumpvars;

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 0; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 0; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x= 1; $display("%4d: x = %b", $time, x);

#10 x = 0; $display("%4d: x = %b", $time, x);

#10 x= 1; $display("%4d: x = %b", $time, x);

#10 $finish;

end

endmodule

// Simulation waveforms