In: Electrical Engineering
Show and classify all potential data hazards.
1. add R2, R5, R4
2. add R4, R2, R5
3. sw R5, 100(R2)
4 . add R5, R2, R4
INSTRUCTION 1 : add R2,R5,R4 ; % Regs[R2] <-- Regs[R5] + Regs[R4] %
The data in registers R5 and R4 are added and the sum stored in Register R2
INSTRUCTION 2 : add R4,R2,R5 ; % Regs[R4] <-- Regs[R2] + Regs[R5] %
The sum data in R2 is added with the data in Register R5, and it further stored in Register R4. Afer this instruction we are losing the original data of R4
INSTRUCTION 3 : sw R5,100(R2) ; % Regs[R5] <-- Mem[100 + Regs[R2] %
The data in the memory location address corresponding to (value in Register R2 plus 100) th location is stored to the Register R5. This will replace original data og Register R5
INSTRUCTION 4 : add R5,R2,R4 ; % Regs[R5] <-- Regs[R2] + Regs[R4] %
The data in Register R2 is added with the data in Register R4 and it is further stored in the Register R5. So by executing this instruction , we are losing the data in Register R5 , which we are moved from the Memory locations in the previous instruction.
There are three situations in which data hazard can occur
1. Read After Write (RAW), a true dependency
2. Write After Read (WAR), an anti-dependency
3. Write After Write (WAW) an output dependecy
when operands are fetched for second operation, the result from the first will not yet have been saved, and hence a data dependency occurs.Therefore, a data dependency (RAW) occurs with instructoin 2, as it is dependent on the completion of instruction 1.
Instruction 3 and Istruction 4 tries to write a destination before it is read by instruction 1 and instructon 2. A Write After Read (WAR) data hazard represents a problem with concurrent execution.Therefore , it must be ensured that the result of Register R5 is not stored before the instruction 3 and instruction 4 has had a chance to fetch the operands.
Instruction 3 and instruction 4 both try to write data into Register R5, therefore A Write After Write (WAW) may occur in concurrent execution.It must be ensured that the Write back of instuction 4 must be delayed until the instruction 1 finishes executing.