In: Electrical Engineering
As an Electrical Engineer, you have been asked to design a receiver that detects a particular sequence of bits transmitted from a remote transmitter. Your system is a MEALY machine that has an input ‘w’ and an output ‘z’ that produces z=1 when the previous two values of w are 00 or 11 otherwise it should give z=0. Please note that there would be only 3 states. Draw the corresponding state diagram and state table.
From the question, I observed that this is a double detection state machine.
Here we will have to cases of detections, which are overlap condition and without overlap condition. State machines are designed for both scenarios..
I have given explanation for state diagrams too.
Please do observe in images.. Thank you.. Have a nice day... :)