Question

Describe what the PROCESS statement does in VHDL. How does that lead to us using the many flip-flops that are in the FPGA?

Answer 1

VHDL is a Hardware description Language where execution of statements are concurrent. However in Behavioral description model of a design, requirement of sequential execution is fulfilled by PROCESS Blocks. Hence all the statements with in PROCESS block are executed sequentially. In architecture block, there may be more than one PROCESS blocks and these all blocks gets executed concurrently.

Statements like IF, CASE, LOOP, WAIT appears within the process body.

Syntax of Process block:

[label] : PROCESS [(sensitivity list)] [is]

declaration of variables;

BEGIN

statemets;

END PROCESS

Sensitivity list is all possible inputs that triggers the PROCESS and causes execution of PROCESS statements. At the END PROCESS, execution is suspended and again gets trigger if sensitivity list signals undergoes an event (can say change).

If sensitivity list is not declared then WAIT statements can be used.

Conditional clauses within the PROCESS blocks infer latch or a Flip Flop i.e. memory.

Conditional assignment statements like IF to any signal translates into a combinational logic in front of a D Flip Flop as an input.