Question

The 8259 can receive ICWs in the sequence ICW1, ICW2, ICW3, ICW4 or ICW1, ICW2, ICW4. How does it know which option is being programmed?

Answer 1

Initialization Control Word 2 (ICW2):

After issuing ICW1 on even address, the PIC is ready to accept initialization Control Word 2. It is issued to an address having A0=1, i.e., on odd address. The format for ICW2 is shown below:

D7 D6 D5 D4 D3 D2 D1 D0

A15/T2 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8

A15-A8 specify the higher byte address of the interrupt for 8080/85 system only. For 8086, T7-T3 are used to specify the interrupt vector type. These bits are inserted in the five most significant bits of the vectoring byte and the 8259A sets the three least significant bits according to the interrupt level as below:

Thus, an 8085A system using a single 8259A could be programmed with only two ICWs; ICW1 & ICW2.

For example, let ICW1 =( 0001 00100 ₂ and

ICW2 =( 0000 0100) ₂

With these initialization command words, the interrupt request inputs are programmed for edge triggered mode. In addition, the 8259A’s priority instruction would be operating in the fully rested mode i.e. IR0 having the highest priority.

Initialization Control Word 3 (ICW3):

This word is required only when there is more than one 8259A in the system and one cascading is used in which case SNGL=0. In master slave configuration mode, the slaves outputs are connected to master interrupt request inputs by the user. Therefore, both the master and the slave must be informed about this interconnection. It is done by issuing ICW3 to 8259A. It will load the 8-bit slave register.

The functions of this register are:

a) The format of ICW3 to be issued to master 8259A is,

D7 D6 D5 D4 D3 D2 D1 D0

S7 S6 S5 S4 S3 S2 S1 S0

If Si =1, IR input has a slave and if Si=0, IR input does not have a slave. If the interrupt controller is set to work as master (either through software or hardware) a ‘1’ is set for each slave in the system. The master will then release byte 1 of the CALL sequence, i.e., CDH (80/85 system only) and will enable the corresponding slave to release bytes 2 and 3 through the address lines. In 86/88 system, the selected slave will release the 2nd byte).

b) If the interrupt controller is used in slave mode, bits D2-D0 identify the slave. The format of control word fir ICW3 issued to slave 8259A is as below:

The three identification bits ID2, ID1, and ID0 tells the slave 8259A to which master input, slave is connected as shown above. The master 8259A releases the 3-bit identification code on local CAS2-CAS0 bus during interrupt acknowledge machine cycle. The slave compares its cascade input with these bits and if they are equal bytes 2 & 3 of the CALL sequence are released by the selected slave on the data bus.

Initialization Control Word 4 (ICW4):

ICW4 is issued to 8259A only if ICW4 bit in ICW1 is set to 1, otherwise the contents of ICW4 are cleared. The format of ICW4 is given below:

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 SFNM BUF MS AEOI ??????

Bits D7-D5 are always set to zero.

Bit D4 (SFNM): If set to 1, the special fully nested mode is used. This mode is utilized in system having more than one 8259A. If set to 0, it is not specific fully nested mode.

Bit D3 (BUF): If BUF is set to 1, the buffered mode is programmed, otherwise non buffered mode. In this mode SP /EN becomes an enable output and the master/slave determination is by M/S.

Bit D2 (M/S): If buffered mode is selected SP /EN is programmed as input. Therefore, master slave configuration is set using M/S bit. M/S=1 means the 8259A is programmed to be a master. M/S =0 means the 8259A is programmed to be a slave. If BUF = 0, M/S has no function.

Bit D1 (AEOI): If AEOI =1, the interrupt controller is programmed automatic end of interrupt mode is programmed.

Bit D0 (??????): This bit is used to set the microprocessor mode. By default the chip is programmed for 8-bit system. If ?????? =1, it sets the 8259A for 8086 system operation. However, to programme other features by ICW4 for 8-bit system ?????? is made 0 which sets 8259A for 8085 system operation.