Question

Write RTL code to design a sequence generator which will generate the sequence : 0,0,1,0,1,1 and repeat . 

(FSM shouldn't be used in RTL) 

Answer 1

module program1 (
input      CLK, RST,
output reg SIG
);

reg [2:0] counter;

// MOD 6 counter geneartion
always @ (posedge CLK)
begin
    if (RST)
       counter <= 3'b0;
    else
       if (counter == 3'd5)
          counter <= 3'd0;
       else
          counter <= counter + 1'b1;
end

// Output generation
always @ (*)
begin
    case(counter)
      3'b000 : SIG = 1'b0;
      3'b001 : SIG = 1'b0;
      3'b010 : SIG = 1'b1;
      3'b011 : SIG = 1'b0;
      3'b100 : SIG = 1'b1;
      3'b101 : SIG = 1'b1;
   endcase
end

endmodule

// Test bench file
module testbench();
reg        CLK, RST;
wire       SIG;

// DUT instantiation
program1 DUT1 (.CLK(CLK), .RST(RST), .SIG(SIG));

// Clock generation
always
   #5 CLK = !CLK;

// Stimulus generation
initial
begin
    CLK = 1'b1;
    RST = 1'b1;
    repeat(2)
      @(negedge CLK);
    RST = 1'b0;
   repeat(15)
      @(negedge CLK);
   $finish;
end

initial begin // dump creation for waveform
$dumpfile("dump.vcd");
$dumpvars;
end

endmodule