Question

Using MARIE RTL, write RTL commands for CALL X and RET Instructions, assume there is an additional register called SP (Stack Pointer)

Answer 1

CALL X ,

here X is the address of subroutine. When call is executed, the control transfers to the subroutine which has the starting address X. Here the content of the PC(which contains the address of the next instruction to be fetched) is to be stored in into the stack. The stack top address is stored in the register SP. i.e, PC content is to be stored into address given by SP. Also PC is to be stored with the address of the subroutine X.

So the operations are: (RTL command for CALL X)

   Execute:                  MBR←PC

                                  MAR ←SP

                                  M[MAR] ←MBR

                                  PC ← X                 (IR[11..0]) will contain address after fetch cycle)

The ret instruction transfers control to the return address located on the stack.The stack pointer SP contains the return address. This address is to be loaded into the PC so that program execution can resume from the instruction after the CALL X.

RET: (RTL command for RET)

                                   PC←SP

                         

The instruction cycle of CALL X

CALL X

Fetch:                       MAR ← PC

MBR ← M[MAR]

   IR ← MBR

PC ← PC + 1

Decode:                    Decode IR[15..12]

                                   MAR ← IR[11..0] // this step is not needed

Get op:                      not needed

Execute:                    MBR←PC

                                  MAR ←SP

                                  M[MAR] ←MBR

                                  PC ← IR[11..0]

Store result: not needed

Initially, PC contains the address of CALL X from where the instruction is to be fetched.

     During fetch cycle, the address in PC loaded into MAR (MAR ← PC) . instruction is fetched from the memory location specified in MAR and stored in MBR(MBR ← M[MAR]). Next instruction in MBR is loaded into IR(IR ← MBR). Meanwhile PC gets incremented to point to next instruction.( PC ← PC + 1)

During Decode cycle, the opcode IR[15..12] is decoded and IR[11..0] contains address X.

During execute cycle, PC content gets saved into memory stack address given by SP and PC is loaded with address X (IR[11..0]).

Instruction cycle of RET

Fetch:                       MAR ← PC

MBR ← M[MAR]

   IR ← MBR

PC ← PC + 1

Decode:                    Decode IR[15..12]

                                   MAR ← IR[11..0] // this step is not needed

Get op:                      not needed

Execute:                    PC←SP

                                 

Store result: not needed