In: Computer Science
Answer
BCLR 0 => Clearing 0th bit in SREG register (carry flag)
BCLR 1 => Clearing 1st bit in SREG register (Zero flag)
BCLR 2 => Clearing 2nd bit in SREG register (Negative flag)
BCLR 3 => Clearing 3rd bit in SREG register (Overflow flag)
BCLR 4 => Clearing 4th bit in SREG register (Sign flag)
BCLR 5 => Clearing 5th bit in SREG register (Half carru flag)
BCLR 6 => Clearing 6th bit in SREG register (Copy storage flag)
BCLR 7 => Clearing 7th bit in SREG register (Disables interrupt)
LDI R19, 0x02 => Loads value 0x02 in R19 => R19 = 0x02
LDI R20, 0x74 => Loads value 0x74 in R20 => R20 = 0x74
LDI R21, 0x04 => Loads value 0x04 in R21 => R21 = 0x04
LDI R22, 0x22 => Loads value 0x22 in R22 => R22 = 0x22
ADD R20, R22 => Add R20 and R22 and Store it into R20 => R20 = 0x74+0x22 = 0x96
SUB R22, R21 => Subtract R21 from R22 and store it into R22 => R22 = 0x22 - 0x04 = 0x1E
ADD R20, R21 => Add R20 and R21 and Store it into R20 => R20 = 0x96+0x04 = 0x9A
MOV R20, R21 => Move R21 value to R20 => R20 = 0x04
JMP DONE => Unconditional Jump
ADD R21, R20 => Skipped
SUB R21, R22 => Skipped
DONE: SUB R20, R21 => Subtract R21 from R20 and store it into R20 => R20 = 0x04 - 0x04 = 0x00
=> Enables Zero Flag in SREG register
Final Values :
R20 = 0x00
R21 = 0x04
SREG = 0x02