Question

Question 3
(a) Identify the location of the following corresponding operand if the address field in an instruction contains decimal value 15.
i. immediate addressing
ii. direct addressing
iii. indirect addressing
iv. register addressing
v. register indirect addressing

(b) Differentiate the characteristics between CISC and RISC architecture.

(c) Discuss the stages involved in fetch-decode-execute cycles.

Answer 1

Solution

Part 1

Immediate	15 is the operand	In immediate addressing mode data is present in address field of instruction
Direct	Data is present in memory location 15	In direct addressing mode the effective address of the data is present in address part of the instruction.So only one memory reference operation is required to access the data.
Indirect	Data is present in the address stored in memory location 15	In this mode address field of instruction contains the address of effective address.So two memory references are required for indirect addressing.
Register	Data is present in the register denoted in the address part of the instruction	In register addressing mode, data is present in the register mentioned in the instruction.
Register Indirect Addressing	Data is prsent in the address stored in the register mentioned in the address part of the instruction	In this mode effective address is in the register, and corresponding register name will be maintained in the address field of an instruction, which requires one register and one memory reference.

Part 2

RISC	CISC
Instructions are simple and standardized	CISC supports complex and variable length instructions.
Small number of fixed length instructions	Large number of instructions.
Instructions take single cycle for execution	Instructions can take several clock cycles.
Pipelining is easy	Pipelining is difficult
RISC uses more registers	CISC uses less number of registers.

Part 3

Fetch Cycle

Program counter stores the address of the next instruction to be executed. In the fetch cycle next instruction is fetched from the memory address that is currently stored in the program counter and stored into the instruction register. When fetch operation ends, the value stored in PC is updated and PC points to the instruction to be executed next. .

Decode Cycle

In this stage, the instruction presented in the instruction register is interpreted by the decoder and also any data required by the instruction is fetched from the memory or register and stored in the Data register

Execute Cycle

This step includes performing arithmetic on operand data or the logical functions and writing the result from accumulator to the memory or register.