Question

Q1 / solve for emitter coupled logic (ECL) :

1) ECL inverter : Study its structure and operation.

2) Study and analyze voltage transfer characteristic (VTC) of the ECL inverter.

3) Study and analyze noise margin of the ECL inverter.

4) Study the static power dissipation of the ECL inverter.

5) Study the propagation delay of the ECL inverter.

6) Design problem: Use ECL to design a 3-input NAND.

Ps : please solve the question in computer not on papers that will be much better, thank you!

Answer 1

A simple ECL inverter from a differential pair:

PART1

Generally a ECL device has coupled transistors of the same type, where no transistor enter saturation, by debenerating the source, and at an input of VCC, Q2 maintains the emitter voltage at a positive voltage.

At Vin = 0V, Q2 doesn,t enter saturation, because voltage VB is chosen slighlty above VEE (generally VEE+VBEon), by avoiding saturation, the inverter becomes much faster, but the degeneration of the emitter and the RC resistor

PART2

With VB=4V:

REE=1.3K

RC=300;

Examine the circuit at Vi=4.4V

The emitter is at 4.4-0.6V=3.8V, thus, the transistor Q2 has VBE=0.2V, which doesn't turn it on, while Q1 conducts:

The output voltage is:

Assuming VBE=0.6

Levels are:

Part 3

Noise margin is reduced, and output doesn't have full swing from the source, meaning it doesn't reach full 5V or 0V, this in exchange of the speed of the inverter, as a reult of the linear operation of the transistors.

Part 4

Current flows through Q1 or Q2, assuming it doesn't flow through both at the same time is appropriate, because of the emitter degeneration, thus, power discipation is: