Model a BCD to 7-Segment Decoder
(1111 1000)
Create a top-level Verilog module, named bcdto7segment_dataflow
with 4-bit data input (x[3:0]),
anode enable output signals (an[3:0]), and 7-bit output
(seg[6:0]) using dataflow modeling (Hint:
You will have to derive seven expressions for the 7 segments on
paper). Assign appropriate logic
to an[3:0] in the model so you can display only on the right
most display.
2. Design a digital circuit, using a decoder, only Nor gates, a
7-segment display, and D Flip Flops, that repeatedly outputs the
sequences of characters ‘P’, ‘E’, ‘A’, ‘L’ if x=0 and ‘L’, ‘E’,
‘A’, ‘P’ if x=1 .
You have access two 7-segment decoder outputs from an existing
circuit. These outputs
show the numbers 00 through 15. Build a circuit to convert the two
7-segment displays,
which display decimal, to one 7- segment display, which displays
the correct
hexadecimal number.
Enter two valid BCD numbers. Show the result in seven segment
display and LED
How to do this using the components dip switch, Two BCD adders
74ls83, And gates, OR gates, 74 ls47 decoder, 7 segment display and
LED
36) Construct BCD counter and draw block diagram of a
three-decade decimal BCD counter.
The following must be included (5points) : -
a) The truth table of BCD counter
b) The implementation of BCD counter
c) The three-decades BCD counter
Design 4-bit odd number synchronous count-down counter showing
BCD output through a 7-segment display using J-K flip flop and
logic gates with Active LOW RESET pin to the existing circuit so
that when RESET pin is enabled, the counter counts from the
beginning
Simulation Project
Design a Seven Segment Decoder to
decode and display CS and the last 2 numbers of your #900 number
(Student ID). Assume the corresponding inputs for the letters and
numbers.
Example: If your #900
number is 900123456 take last 2 numbers that is 56 and display
'CS56'
Inputs Assumptions
00- for C
01-for S
10— Last number (6 in the given
example)
11— Last but one number (5 in the
given example)
Write the Truth Table for the...