Question

4.16 Inthisexercise,weexaminehowpipeliningaffectstheclockcycletimeofthe processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:
250ps 350ps 150ps 300ps 200ps
Also, assume that instructions executed by the processor are broken down as follows:
45% 20% 20% 15%
4.16.1 [5] <§4.5> What is the clock cycle time in a pipelined and non-pipelined processor?
4.16.2 [10]<§4.5>WhatisthetotallatencyofanLDURinstructioninapipelined and non-pipelined processor?
4.16.3 [10] <§4.5> If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?
4.16.4 [10]<§4.5>Assumingtherearenostallsorhazards,whatistheutilization of the data memory?
4.16.5 [10]<§4.5>Assumingtherearenostallsorhazards,whatistheutilization
of the write-register port of the “Registers” unit?

Answer 1

1. For the pipelined processor, the clock cycle time is determined by the slowest stage i.e 350 ps.

For the non-pipelined processor, the clock cycle time is given as the sum of latencies all stage i.e

250+350+150+300+200= 1250 ps

2. Pipelining enhances the latency as compared to non-pipelined system.

So, For non-pipelined processor latency will remain same i.e 1250ps.

For pipelined processor latency is given as number of stages * cycle time i.e 5*350= 1750ps

3. Split ID into two stages with (350/2)=175ps. Now the new clock cycle time of the processor = 300 ps since this become the new longest latency in datapath.

If we conside instructions executed by the following operation by processor :
Alu 45%

beq 20%

lw 20%

sw 15%

4. Data memory is utilized by lw and sw instructions, so the utilization will be = (20+15) i.e 35% of the clock cycle

5. Write-register port is generally used by ALU and lw instructions, so theutilization will be = (45+20) i.e 65% of the clock cycle.