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In: Computer Science

note (Please solve the questions in the language of operating systems) [2] (i) Define Timesharing.    ...

note (Please solve the questions in the language of operating systems)

[2] (i) Define Timesharing.

    (ii) In a one processor system, there is an interrupt clock which is set to a “time slice Q”, that is, every Q an interrupt occurs to stop the process. There is only one I/O device in the system    which is interrupted when the process needs an I/O. There are 3 processes A, B, C.

    

     Process A executes an I/O interrupt every T units of time.

     Process B executes an I/O interrupt every 2T units of time.

     Process C executes an I/O interrupt every 3T units of time.

(a) Which of the above processes will benefit the most and which is not when Q = T.

      Explain your answer

(b) Which of the above processes will benefit the most and which is not when Q = 2T.

      Explain your answer

(a) Which of the above processes will benefit the most and which is not when Q = 3T.

      Explain your answer

What is the best value should Q takes for good performance ? explain your answer in full.

[3] (a) Define DMA (Direct Memory Access).

      (b) An input device can transmit 100 characters every 4 mils 10 , if the CPU needs 2 mics to service the

            Interrupt. How much time is left for asynchronous I/O. What if it can transmit 1000 characters

            every 4 mils and the CPU also needs 2 mics for the service routine.

            What do you think? Explain your answer in details.

[4] (a) What is the interrupt types? Give examples.

      

       (b) What type of interrupt the following pieces of code in C might generate. Explain your answer.

(i)

int n = 0;

while (n = 0)

  printf(“Hello”);

            (ii)

           

            int n = 1 , m = 0, x = 10;

            while (n/!x<0.001)

                 { m +=x;

                   n++;

                 }

           

           

       [5] Draw clearly explaining briefly what is happening the following:

           

  1. Interrupt Vector
  2. Instruction Cycle with instruction cash register.
  3. System Queues and Scheduling.

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