A RISC processor that uses the five-stage instruction fetch and execution design is driven by a...

A RISC processor that uses the five-stage instruction fetch and execution design is driven by a 1-GHz clock. Instruction statistics in a large program are as follows:

Branch 20%

Load 30%

Store 10%

Computational instructions 40%

Please answer the following questions.

1-Assume 80% of the memory access operations are in the cache, and 20% are in the main memory. A cache miss has a 3-cycle penalty. What is the instruction throughput for non-pipelined execution?

2- Assume there are an instruction cache and a data cache. For both caches, a cache miss stalls the pipeline for 3 cycles. Assume the cache hit rate for the instruction cache is 85%. 80% of the Load instructions load data from the data cache, while 20% of them load data from the main memory. 40% of the Store instructions store data into the data cache, while 60% of them store data into the main memory. What is the instruction throughput for pipelined execution?

3-Assume all memory accesses are cache hit. 20% of the Load instructions are followed by a dependent computational instruction, and 30% of the computational instructions are also followed by a dependent computational instruction. 20% of the branch instructions are unconditional, while 80% are conditional. 40% of the conditional branches are taken, 60% are not taken. The penalty for taking the branch is one cycle. If data forwarding is allowed, what is the instruction throughput for pipelined execution?

Expert Solution

venereology answered 4 months ago

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