Question

F = (AB' +A'B)(C+ D') Implement F with AND-OR gates (denoted as F1)

Implement F with multi-level NAND gate circuit (denoted as F2)

Implement F with multi-level NOR gate circuit (denoted as F3)

Verify F1 = F2 = F3 (using Verilog Structural level modeling)

Answer 1

Given F = (AB' +A'B)(C+ D')

F = AB'(C+ D') +A'B(C+ D')

F = (AB'C+ AB'D') +(A'BC+ A'BD')

F = AB'C + A'BC + AB'D' + A'BD'

Simplified Circuit: Given F = AB'C + A'BC + AB'D' + A'BD'

Explanation:
Negation(¬) of any logical Identity P is Nothing but Opposite Truth Value for P. i.e If P is T then (¬P) is F
And gate is used to find the Product of Two literals P AND Gate Q Output is PQ
OR gate is used to find the Sum of Two literals P OR Gate Q Output is P+Q

2) Given F = AB'C + A'BC + AB'D' + A'BD'

[F']' = [(AB'C + A'BC + AB'D' + A'BD')']'  { We know that (P')'= P }

F = [(AB'C)'(A'BC)'(AB'D' )'(A'BD')']'  { We know that (P+Q)'= P' Q' }

F = [(AB'C)'(A'BC)'(AB'D' )'(A'BD')']'

Simplified Circuit:Given F = [(AB'C)'(A'BC)'(AB'D' )'(A'BD')']'

Explanation:
NAND gate is used to find the Product of Two literals P NAND Gate Q Output is (PQ)'

3) Given F = AB'C + A'BC + AB'D' + A'BD'

[F']' = [(AB'C + A'BC + AB'D' + A'BD')']'  { We know that (P')'= P }

F = [(AB'C)'(A'BC)'(AB'D' )'(A'BD')']'  { We know that (P+Q)'= P' Q' }

F = [(AB'C)'(A'BC)'(AB'D' )'(A'BD')']'

F = [(A'+B+C')(A+B'+C')(A'+B+D)(A+B'+D)]' { We know that (PQ)'= P' + Q' }

F = [(A'+B+C')'+(A+B'+C')'+(A'+B+D)'+(A+B'+D)'] { We know that (PQ)'= P' + Q' }

[F']' = {[(A'+B+C')'+(A+B'+C')'+(A'+B+D)'+(A+B'+D)']'}'  { We know that (P')'= P }

F = {[(A'+B+C')'+(A+B'+C')'+(A'+B+D)'+(A+B'+D)']'}'

Explanation:
NOR gate is used to find the Sum of Two literals P NOR Gate Q Output is (P+Q)'