Given a Boolean function: f(a,b,c,d) =
m(1,6,7,10,12)+dc(3,4,9,15). i) Design a circuit for implementing
f(a,b,c,d) with ONE 4-to-1 MUX and other basic logic gates. USE a
and b as select inputs. ii) Draw the circuit. iii) Write the VHDL
code for a 4-to-1 MUX, named “mux_4to1”, with input: a, b, c, d,
s0, s1; and output: z. iv) Write the complete VHDL code for the
above circuit in part (iii), named “Boolean_MUX”.