Question

Explain about the role of "bus" in Von Neumann architecture. Why a slow bus-speed can cause a performance-bottleneck in Von Neumann architecture?

Answer 1

ROLE OF BUS IN VON NEUMANN ARCHITECTURE:

Buses are the methods by which information is sent starting with one part of a PC then onto the next, interfacing all major internal components to the CPU and memory.

There are 3 types of Buses-

1. Control Bus

2. Data Bus

3. Address Bus

1. Control Bus:

Conveys control signals/orders from the CPU (and status signals from different gadgets) in order to control and coordinate all the exercises inside the PC.

2. Data Bus:

Carries data between the processor, the memory unit and the input/output devices.

3. Address Bus:

Conveys the addresses of information (however not the information) between the processor and memory.

Slow bus-speed can cause a performance-bottleneck in Von Neumann architecture:

The Von Neumann bottleneck is a characteristic consequence of utilizing a Bus to move information between the processor, memory, long term storage, and fringe gadgets. Regardless of how quick the Bus plays out its errand, overpowering it — that is, framing a bottleneck that diminishes speed — is consistently conceivable. After some time, processor speeds keep on expanding while memory and other gadget upgrades center around thickness — the capacity to store more in less space. Subsequently, the bottleneck turns out to be a greater amount of an issue with each improvement, making the processor invest a ton of energy being inactive.

Sensibly speaking, you can conquer a portion of the issues that encompass the Von Neumann bottleneck and produce little, however recognizable, speeds up. Here are the most widely recognized arrangements:

Caching: When issues with acquiring information from memory quick enough with the Von Neumann Architecture got clear, equipment sellers immediately reacted by including restricted memory that didn't need transport access. This memory seems outer to the processor however as a feature of the processor bundle. Fast store is costly, be that as it may, so reserve sizes will in general be little.

Processor Caching: Unfortunately, outer reserves actually don't give enough speed. In any event, utilizing the quickest RAM accessible and removing the transport access totally doesn't meet the handling limit needs of the processor. Subsequently, merchants began including inside memory — a store littler than the outside reserve, however with much quicker access since it's aspect of the processor.

Prefetching: The issue with stores is that they demonstrate helpful just when they contain the right information. Lamentably, store hits demonstrate low in applications that utilization a ton of information and play out a wide assortment of undertakings. The subsequent stage in making processors work quicker is to figure which information the application will require straightaway and burden it into reserve before the application requires it.

Utilizing specialty RAM: You can get covered by RAM letters in order soup on the grounds that there are a larger number of sorts of RAM than the vast majority envision. Every sort of RAM indicates to unravel in any event part of the Von Neumann bottleneck issue, and they accomplish work — inside cutoff points. Much of the time, the upgrades spin around getting information from memory and onto the transport quicker. Two significant (and numerous minor) factors influence speed: memory speed (how quick the memory moves information) and dormancy (how long it requires to find a specific bit of information). Peruse more about memory and the elements that influence it.