In: Computer Science
Considering the following sequence of MIPS code, your task is to use pipelining building blocks to execute this set of instructions.
add $R2, $R0, $R0
lw $R1, 0($R2)
addi $R3, $R1, 20
add $R1, $R2, $R0
or $R1, $R2, $R0
A)
How many stall cycles would occur in a MIPS pipelining without Pipeline Forwarding? Using the pipelining building blocks to explain your result.
B)
How many stall cycles would occur in a MIPS pipelining with Pipeline Forwarding? We assume that Pipeline Forwarding exists between DM-to-ALU, ALU-to-ALU, and DM-to- DM. Using the pipelining building blocks to explain your result.
Answer A
Without DATA forwarding, if there is any dependency on previous instruction, stall will be taken.
Instruction | CC1 | CC2 | CC3 | CC4 | CC5 | CC6 | CC7 | CC8 | CC9 | CC10 | CC11 | CC12 | CC13 |
add $R2, $R0, $R0 | IF | ID | ALU | MEM | WB | ||||||||
lw $R1, 0($R2) | IF | ID | STALL | STALL | ALU | MEM | WB | ||||||
addi $R3, $R1, 20 | IF | STALL | STALL | ID | STALL | STALL | ALU | MEM | WB | ||||
add $R1, $R2, $R0 | STALL | STALL | IF | STALL | STALL | ID | ALU | MEM | WB | ||||
or $R1, $R2, $R0 | STALL | STALL | IF | ID | ALU | MEM | WB |
Total 4 stalls
Answer B
With DATA forwarding, DM-to-ALU, ALU-to-ALU, and DM-to- DM. DM means MEM stage
Instruction | CC1 | CC2 | CC3 | CC4 | CC5 | CC6 | CC7 | CC8 | CC9 |
add $R2, $R0, $R0 | IF | ID | ALU | MEM | WB | ||||
lw $R1, 0($R2) | IF | ID | ALU | MEM | WB | ||||
addi $R3, $R1, 20 | IF | ID | ALU | MEM | WB | ||||
add $R1, $R2, $R0 | IF | ID | ALU | MEM | WB | ||||
or $R1, $R2, $R0 | IF | ID | ALU | MEM | WB |
with data forwarding there is 0 stalls. ALL the dependencies will be handled using ALU-to-ALU transfer.