Question

This question concerns a synchronous sequential counter, which counts an arbitrary

sequence. The properties of the counter include the following:

1. The counter has two inputs, input X and CLK (Clock), and three outputs, A, B and

C. A is the most significant digit in the counting value, and C is the least

significant digit.

2. The counter counts under a POSITIVE clock edge.

3. When X is 0, the counting sequence is:

1, 6, 3, 2, 5, 1, 6, 3, 2, 5, 1, …

When X is 1, the counting sequence is:

1, 5, 7, 0, 3, 1, 5, 7, 0, 3, 1, …

(a) Write down the state table of your counter. You can assume that the states that do

not occur are don’t care conditions.

(b) Design the counter using positive-edged triggered JK flip-flops. Show your design

steps clearly in your work. As the final result, draw the logic circuit diagram of

your counter.

Answer 1

Outputs are taken at output of each flip-flop.

The flip-flops considered are positive edge flip-flops and I used EXOR and EXNOR gates. If you don't wish, you can replace it by basic gates.

Hope you got it