Question

verilog question

Please answer true or false:

The expression(A==B)is evaluated as true if A is equal to B and false other wise .The !=operator has the opposite effect.

true or false?

For background reference only:

Write a verilog code for 16:1 multiplexer and create a test bench for the 15th input to be selected by control input to be on output line.

Answer 1

DESIGN MODULE FOR 16:1 MUX

module multix16( sel, i, q );

input[3:0] sel;// 4 select lines
input[15:0] i; //INPUTS
output q;

wire q;
wire[3:0] sel;
wire[15:0] i;

assign q = i[sel];

endmodule

TESTBENCH MODULE FOR 16:1 MUX
module multix16_tb;

reg[15:0] i;
reg[3:0] sel;
wire q;

integer x;

multix16 my_mux( sel, i, q );

initial
begin
i[14]=1;#1 //15th input is being set 1 here


sel = 14; #1; //Sel line set to 14 for selecting 15th input set above
#1 $monitor("i = %b", i, " | sel = ", sel, " | q = ", q );
$display("-----------------------------------------");

end
endmodule

OUTPUT SCREENSHOT