Question

Can someone explain how to manipulate the clock in verilog code? For example, I do not understand how to go from 100MHz to 68027Hz.

Answer 1

so for out_clk low "0" period I used the counter named clock_count to count between range (000-2DF)

And

For out_clk high "1" period I used the clock_count to count between range (2DE - 5BE )

Verilog code for clock converter from 100M Hz to 68027 Hz

// Code your design here
module clock_converter(in_clk,out_clk);
  
  
input in_clk;
  
output out_clk;
  
reg [10:0] clock_count=11'b0;
  
  
always @(posedge in_clk)
begin
if(clock_count == 11'b10110111110)// clock_count==5BE
clock_count <= 11'b0;
else
clock_count <= clock_count+1'b1;
  
end
  
assign out_clk = (clock_count<11'b01011011111)?1'b0:1'b1;

  
endmodule
  

//testbench

// Code your testbench here
// or browse Examples
module test ;
  
reg in_clk;
  
wire out_clk;
  
clock_converter dut (in_clk,out_clk);
  
initial
begin
in_clk = 1'b0;
forever #5 in_clk = ~in_clk;
end
  
initial
begin
$dumpfile("dump.vcd");
$dumpvars;
#1000000000000;
$finish;
end
endmodule

// Simulated waveform

Clock_count observation at 1 -> 0 transition

Clock_count observation at 0 - > 1 transition