Question

In: Electrical Engineering

Create an integer to std_logic_vector function(i2std)

Expert Solution

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------- I2STD using NUMERIC_STD

------- Replace 7 with desired vector length

use ieee.numeric_std.all;

signal in_1 : integer;

signal out_1 : std_logic_vector(7 downto 0);

signal out_2 : std_logic_vector(7 downto 0);

---- Conversion of positive integers or unsigned integers

out_1 <= std_logic_vector(to_unsigned(in_1, out_1'length));

---- Conversion of positive or negative integers or signed integers

out_2 <= std_logic_vector(to_signed(in_1, out_2'length));

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------- I2STD USING STD_LOGIC_ARITH

------- Replace 7 with desired vector length

-----Conversion of integer to unsigned std_logic_vector

use ieee.std_logic_arith.all;

signal in_1 : integer;

signal out_1 : unsigned(7 downto 0);

out_1 <= conv_unsigned(in_1, out_1'length);

--------Conversion from integer to std_logic_vector

------- When a negative number is inputted, the result will be in 2's complement vector.

signal in_2 : integer;

signal out_2 : std_logic_vector(7 downto 0);

out_2 <= conv_std_logic_vector(in_2, out_2'length);

----Conversion of integer to signed std_logic_vector

signal in_3 : integer;

signal out_3 : signed(7 downto 0);

out_3 <= conv_signed(in_3, out_3'length);

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Manojponduru answered 2 years ago

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