Question

Verilog coding

module demux (

En, I0, I1, Y0, Y1, Y2, Y3 );

input En, I0, I1;

output reg Y0, Y1, Y2, Y3;

// Your behavioral description of Y

// using if-else or case statements

endmodule

Answer 1

Verilog code:

module demux (

En, I0, I1, Y0, Y1, Y2, Y3 );

input En, I0, I1;

output reg Y0, Y1, Y2, Y3;

always @(En,I0,I1)

begin

if(En == 0)

begin

Y0=1'b0;

Y1=1'b0;

Y2=1'b0;

Y3=1'b0;

end

else if (I1==0 && I0==0)

begin

Y0=1'b1;

Y1=1'b0;

Y2=1'b0;

Y3=1'b0;

end

else if (I1==0 && I0==1)

begin

Y0=1'b0;

Y1=1'b1;

Y2=1'b0;

Y3=1'b0;

end

else if (I1==1 && I0==0)

begin

Y0=1'b0;

Y1=1'b0;

Y2=1'b1;

Y3=1'b0;

end

else if (I1==1 && I0==1)

begin

Y0=1'b0;

Y1=1'b0;

Y2=1'b0;

Y3=1'b1;

end

end

endmodule

RTL Schematic:

Test Bench:

module dmuxtb;

// Inputs

reg En;

reg I0;

reg I1;

// Outputs

wire Y0;

wire Y1;

wire Y2;

wire Y3;

// Instantiate the Unit Under Test (UUT)

demux uut (

.En(En),

.I0(I0),

.I1(I1),

.Y0(Y0),

.Y1(Y1),

.Y2(Y2),

.Y3(Y3)

);

initial begin

// Initialize Inputs

En = 0;

I0 = 0;

I1 = 0;

// Wait 100 ns for global reset to finish

#100;

En = 1;

I0 = 0;

I1 = 0;

#100;

En = 1;

I0 = 0;

I1 = 1;

#100;

En = 1;

I0 = 1;

I1 = 0;

#100;

En = 1;

I0 = 1;

I1 = 1;

#100;

  

// Add stimulus here

end

  

endmodule

Simulation: