Question

Design a controller that detects the four-bit, binary MSB first serial sequence of the rounded average of the last digits of the team members' Social Security Numbers. You should use a switch in the Nexys4 DDRTM FPGA Board to mimic a clock pulsed. The input bit should be setup before the clock pulse

Verilog Code

Answer 1

Introduction:an algorithmic state machine (ASM) is a finite state Machine that use a sequential circuit (the controller)

to coordinate a series of operations among other functional units functional units such as counters,registers,adders,etc.(the Datapath).The series of operations implement an algorithm.the controllers passes "control" signals which can be moore or mealy outputs from the controllers ,to the datapath.The datapath returns informations to the controller in the form of "status" information that can be used to determine the consequences of states in the conntroller.both the controller and the datapath may each have external inputs and outputs and are clocked simultaneously.

the two basic stratigies for the design of a controller are:

1.hardwired control: which includes techniques such as "one hot state" (also known as "one flipflop per state ")and decoded sequences registers.

2.microprogrammed control:which usesa memory device to produce a sequence of control words to datapath..since hardwired control is generally speaking,fast compared with microprogramming stratagies,most modern micrprocessor helps in the course for now we concentrate on a binary multiplier.

Binary Multiplication:the design of binary multiplication stratigies has long history.Multiplication is such a fundemental and frequently used operation in digital signal processing,that most modern DSP chips have decided multiplication hardware to maximize performance.the first example that we considered(in class)that used a repeated addition strategy of clock multiplier the more iterations that are required.That is not practical.another approach to achieve fast corresponding bits.for an 8-bit x8-bit multiplier ,a(2 8+8)x16=1 Mbit memory is required.This approach is conceptually simplified time equal to the access time of the memory device ,regardless of the data being multiplied . But it is also impratical for larger values of n .