PWrite a VHDL function that accepts a vector of arbitrary length and integer that specifies the...

PWrite a VHDL function that accepts a vector of arbitrary length and integer that specifies the number of bits the input vector to be rotated to the left and returns another vector. For instance functions accepts two inputs: 0101011 and 3 and it returns 1011010.

Expert Solution

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity vec_function is
   generic ( N   : integer := 6);
   port (   din   : in std_logic_vector(N-1 downto 0);
       rotate   : in integer;
       dout   : out std_logic_vector(N-1 downto 0)
   );
end vec_function;

architecture arch of vec_function is

begin

dout <= (din ((N - 1) - rotate downto 0) & din((N - 1) downto (N - rotate)));

end arch;

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--Simulated on ModelSim

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