Question

Overview

In this assignment you are required to implement binary code comparator using Xilinx that it is compatible with the MXK Seven Segment Displays. You will draw your digital logic circuit using Xilinx and then simulate it to verify the functionality of your design.

Software Requirements

? Xilinx ISE 10.1 or higher

Specifications

Binary Code Comparator

The binary code comparator is to be implemented and made compatible with the seven 7-segment displays of the board. Represent the first five digits of your student number into binary. If a given decimal digit is odd, then the binary equivalent will be 1, otherwise it will be 0. For example, the student (decimal) number 99805234 will produce 11001. The user is to enter a 5-bit binary sequence one bit at a time. The five bits will be displayed on five of the seven segment displays. If the five entered bits equal to the stored binary code, then ‘E’ is to be displayed on the sixths seven- segment display. However, if the five entered bits do not equal the binary code, then ‘n’ is to bedisplayed. Note that you do not have to display bits as they are received in accumulating manner (as shown in the figure below), rather, you can display all five bits and the comparator outcome (‘E’ or ‘n’) when the fifth bit is received. All six seven-segment displays are to stay on for five seconds, then they will be erased. Once the displays are erased, the circuit will be ready for receiving a new set of five input bits.

- Reset: if pressed, the circuit will return to the initial state and all seven segment displays are to be erased.

- Input (could be received from a dipswitch in your MXK): to specify the binary input (1 or 0).

- Trigger (could be received from a pushbutton in your MXK): to allow the input to be received by the circuit.

- Clock: to alternate between the 7-segment displays (expected to be around 1000 Hz).

There are two sets of outputs, which are:

- d1, d2, ..., d7 (anodes to switch between the seven 7-segment displays)

Answer 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity seven_segment_display_VHDL is
   Port ( clock_1000hz : in STD_LOGIC;-- 1000hz clock on Basys 3 FPGA board
          reset : in STD_LOGIC; -- reset
          Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals
          LED_out : out STD_LOGIC_VECTOR (6 downto 0));-- Cathode patterns of 7-segment display
end seven_segment_display_VHDL;

architecture Behavioral of seven_segment_display_VHDL is
signal one_second_counter: STD_LOGIC_VECTOR (27 downto 0);
-- counter for generating 1-second clock enable
signal one_second_enable: std_logic;
-- one second enable for counting numbers
signal displayed_number: STD_LOGIC_VECTOR (15 downto 0);
-- counting decimal number to be displayed on 4-digit 7-segment display
signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0);
signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0);
-- creating 10.5ms refresh period
signal LED_activating_counter: std_logic_vector(1 downto 0);
-- the other 2-bit for creating 4 LED-activating signals
-- count         0 -> 1 -> 2 -> 3
-- activates    LED1 LED2 LED3   LED4
-- and repeat
begin
-- VHDL code for BCD to 7-segment decoder
-- Cathode patterns of the 7-segment LED display
process(LED_BCD)
begin
   case LED_BCD is
   when "0000" => LED_out <= "0000001"; -- "0"     
   when "0001" => LED_out <= "1001111"; -- "1"
   when "0010" => LED_out <= "0010010"; -- "2"
   when "0011" => LED_out <= "0000110"; -- "3"
   when "0100" => LED_out <= "1001100"; -- "4"
   when "0101" => LED_out <= "0100100"; -- "5"
   when "0110" => LED_out <= "0100000"; -- "6"
   when "0111" => LED_out <= "0001111"; -- "7"
   when "1000" => LED_out <= "0000000"; -- "8"     
   when "1001" => LED_out <= "0000100"; -- "9"
   when "1010" => LED_out <= "0000010"; -- a
   when "1011" => LED_out <= "1100000"; -- b
   when "1100" => LED_out <= "0110001"; -- C
   when "1101" => LED_out <= "1000010"; -- d
   when "1110" => LED_out <= "0110000"; -- E
   when "1111" => LED_out <= "0111000"; -- F
   end case;
end process;
-- 7-segment display controller
-- generate refresh period of 10.5ms
process(clock_1000hz,reset)
begin
   if(reset='1') then
       refresh_counter <= (others => '0');
   elsif(rising_edge(clock_1000hz)) then
       refresh_counter <= refresh_counter + 1;
   end if;
end process;
LED_activating_counter <= refresh_counter(19 downto 18);
-- 4-to-1 MUX to generate anode activating signals for 4 LEDs
process(LED_activating_counter)
begin
   case LED_activating_counter is
   when "00" =>
       Anode_Activate <= "0111";
       -- activate LED1 and Deactivate LED2, LED3, LED4
       LED_BCD <= displayed_number(15 downto 12);
       -- the first hex digit of the 16-bit number
   when "01" =>
       Anode_Activate <= "1011";
       -- activate LED2 and Deactivate LED1, LED3, LED4
       LED_BCD <= displayed_number(11 downto 8);
       -- the second hex digit of the 16-bit number
   when "10" =>
       Anode_Activate <= "1101";
       -- activate LED3 and Deactivate LED2, LED1, LED4
       LED_BCD <= displayed_number(7 downto 4);
       -- the third hex digit of the 16-bit number
   when "11" =>
       Anode_Activate <= "1110";
       -- activate LED4 and Deactivate LED2, LED3, LED1
       LED_BCD <= displayed_number(3 downto 0);
       -- the fourth hex digit of the 16-bit number    
   end case;
end process;
-- Counting the number to be displayed on 4-digit 7-segment Display
-- on Basys 3 FPGA board
process(clock_1000hz, reset)
begin
       if(reset='1') then
           one_second_counter <= (others => '0');
       elsif(rising_edge(clock_1000hz)) then
           if(one_second_counter>=x"5F5E0FF") then
               one_second_counter <= (others => '0');
           else
               one_second_counter <= one_second_counter + "0000001";
           end if;
       end if;
end process;
one_second_enable <= '1' when one_second_counter=x"5F5E0FF" else '0';
process(clock_1000hz, reset)
begin
       if(reset='1') then
           displayed_number <= (others => '0');
       elsif(rising_edge(clock_1000hz)) then
            if(one_second_enable='1') then
               displayed_number <= displayed_number + x"0001";
            end if;
       end if;
end process;
end Behavioral;

BCD to Seven segment display::

process(LED_BCD)
begin
   case LED_BCD is
   when "0000" => LED_out <= "0000001"; -- "0"     
   when "0001" => LED_out <= "1001111"; --

"1"
   when "0010" => LED_out <= "0010010"; -- "2"
   when "0011" => LED_out <= "0000110"; -- "3"
   when "0100" => LED_out <= "1001100"; -- "4"
   when "0101" => LED_out <= "0100100"; -- "5"
   when "0110" => LED_out <= "0100000"; -- "6"
   when "0111" => LED_out <= "0001111"; --

"7"
   when "1000" => LED_out <= "0000000"; -- "8"     
   when "1001" => LED_out <= "0000100"; -- "9"
   when "1010" => LED_out <= "0000010"; -- a
   when "1011" => LED_out <= "1100000"; -- b
   when "1100" => LED_out <= "0110001"; -- C
   when "1101" => LED_out <= "1000010"; -- d
   when "1110" => LED_out <= "0110000"; -- E
   when "1111" => LED_out <= "0111000"; -- F
   end case;
end process;