Question

Design a sense amplifier for a 4 words of 4 bits SRAM. Using CMOS.

Digital Electronics.

Answer 1

Modern digital systems require the capability of storing and retrieving large amounts of information at high speeds. Memories are circuits or systems that store digital information in large quantity. This chapter addresses the analysis and design of VLSI memories, commonly known as semiconductor memories. Today, memory circuits come in different forms including SRAM, DRAM, ROM, EPROM, E2PROM, Flash, and FRAM. While each form has a different cell design, the basic structure, organization, and access mechanisms are largely the same [1-6]. In this paper, we present an analysis of the Read/ Write timings of SRAM using 6-T SRAM Cell, a latch-based Sense Amplifier and other peripheral circuitry in 90nm CMOS Technology

Recent surveys indicate that roughly 30% of the worldwide semiconductor business is due to memory chips [7-9]. Over the years, technology advances have been driven by memory designs of higher and higher density. Electronic memory capacity in digital systems ranges from fewer than 100 bits for a simple function to standalone chips containing 256 Mb (1 Mb _ 210 bits) or more.1 Circuit designers usually speak of memory capacities in terms of bits, since a separate flip-flop or other similar circuit is used to store each bit. On the other hand, system designer’s usually state memory capacities in terms of bytes (8 bits); each byte represents a single alphanumeric character [10-12]. Very large scientific computing systems often have memory capacity stated in terms of words (32 to 128 bits). Each byte or word is stored in a particular location that is identified by a unique numeric address. Memory storage capacity is usually stated in units of kilobytes (K bytes) or megabytes (M bytes). Because memory addressing is based on binary codes, capacities that are integral powers of 2 are most common. Thus the convention is that, for example, 1K byte 1,024 bytes and 64K bytes _ 65,536 bytes. In most memory systems, only a single byte or word at a single address is stored or retrieved during each cycle of memory operation. Dual-port memories are also available that have the ability to read/write two words in one cycle [2-4].

PROPOSED DESIGN OF 6-T FAST RAM The schematic of Read circuitry used in the proposed design is shown in Fig-1. Read enable (RE) signal is given as common input to two NAND gate while BL and BLbar becomes other two inputs for the gate. Push pull configuration of transistors finally drive the Data input line. Basic NAND gate design strategy is used to design transistors. All the transistors of the NAND gate has common W/L ratio. Transistors M9 and M10 have twice the width of Transistor M3 and M4. Write circuit should be able to force the BL and BLbar line to change its state as per the given input data by charging the large bit line capacitances instantaneously. Hence write circuit is designed with NOR gates to provide higher current driving capability. Transistor level schematic is shown in Fig-2. The circuit resembles the read circuit with NAND gate replaced by NOR gates. Write enable (WE) signals control the write operation. Output of each NAND gate is driven by NMOS transistor having higher W/L ratio. These two transistors drive BL and BLbar lines.

Row Decoder In the case of row decoder, PMOS is activated by precharge control signal PEbar prior to the address decoding process. All word line (WL) is pulled high to VDD during precharge. Column (or block) decoders have to provide the discharge path from the precharged bit line to the sense amplifier during read operation. The same lines should be able to drive the bit line to write either 0 or 1 to the memory SRAM cell. Read and write access time of the memory is primarily restricted by the propagation delay of the decoder. Decoder outputs are connected throughout the memory cell making long interconnections which are main resources of delay and higher power consumption. A 2:4 row decoder used in this design is shown

  In this design MSB of Row address controls enable of sense amplifiers. When MSB=0, first row of sense amplifiers will be enabled during read operation. Similarly when MSB=1, other row of sense amplifiers will be enabled during read operationTo ensure read stability of the 6T cell shown below in Fig-4, the voltage across M8 should be less than the threshold voltage when the charge on BLBAR is discharged through M8 and M11. Intuitively, read stability can be met by choose the size of M8 to be greater M11. The exact size of M8 can be determined from the CR has to be greater than 1.2 to ensure read stability. A CR value of 1.5 is chosen for the design of 6T cell.

To ensure write stability, the voltage across M10 should be less than the threshold voltage when BL is pulled low to write a ‘0’ into the 6T cell. Similarly to read stability, the exact size of M10 can be determined from the pull-up ratio (PR), where CR has to be at least less than 1.8 to ensure read stability. A CR value of 1 is chosen for the design of 6T cell. The end result of transistor sizing after stability analysis is shown below: W4 = W5 = W10 = W11 minimum layout width = 0.48µm W8 = W9 = 1.5W5 = 0.72µm