Question

The objective of this lab is to practice your Verilog coding and the design of a Finite State Machine. Lab Goal: For this lab, you will code a Verilog module to implement the FSM described in this document. This lab will also require that you use the Seven - Segment Display on the DE0 - CV FPGA board. Design Specifications for the FSM Implem ent the following simple state machine on the DE0 - CV FPGA board. This FSM will have 5 states. The clock to this FSM will be provided by yourself using KEY0 (one of the push buttons on the board). Include a debounce module in your code but do not use it. S o you write the code as described in the lecture, but there should be no debounce module instance. I want you to understand this module but it is unnecessary on our board. The transitions from any one state to another are determined by switches 0 through 4 of the board (SW0, SW1, SW2, SW3, and SW4) as shown in the state diagram below. This will be easier than using pushbuttons for the inputs to switch to states. That means you set the switch and then clock it using KEY0. It really only matters what the swi t ch positions are when the clock edge occurs. NOTE reiterating this use slide s witches not pushbuttons for input. Use KEY0 for the clock, and generate the clock signal by hand by pushing KEY0. Any input transition not explicitly referenced in the diagram keeps the machine in the same state. Moreover, if two or more switches are asserted simultaneous ly, no transition should occur. SW0 acts as the rese t and should reset the FSM to S 00 regardless of all other switches or the pushbutton. (note you could use K EY1 pushbutton instead but it isn’t clear that would be better). How to write your code: Study Lecture 9 section 3 on how to write a Finite State Machine in Verilog. Your code will have two parts. There will be a synchronous part which is the part models the flip flops. An example of this is Lecture 9 slide 33. The other part is the combinatorial part, which is the part that feeds the inputs to the flip flops, that is like the code in Lecture 9 slides 29 through 32. This i

Answer 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcd_7seg is
Port ( B0,B1,B2,B3 : in STD_LOGIC;
A,B,C,D,E,F,G : out STD_LOGIC);
end bcd_7seg;

architecture Behavioral of bcd_7seg is

begin

A <= B0 OR B2 OR (B1 AND B3) OR (NOT B1 AND NOT B3);
B <= (NOT B1) OR (NOT B2 AND NOT B3) OR (B2 AND B3);
C <= B1 OR NOT B2 OR B3;
D <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3) OR (B1 AND NOT B2 AND B3) OR (NOT B1 AND B2) OR B0;
E <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3);
F <= B0 OR (NOT B2 AND NOT B3) OR (B1 AND NOT B2) OR (B1 AND NOT B3);
G <= B0 OR (B1 AND NOT B2) OR ( NOT B1 AND B2) OR (B2 AND NOT B3);

end Behavioral;

VHDL Code for BCD to 7 segment display using Case Statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcd_7segment is
Port ( BCDin : in STD_LOGIC_VECTOR (3 downto 0);
Seven_Segment : out STD_LOGIC_VECTOR (6 downto 0));
end bcd_7segment;

architecture Behavioral of bcd_7segment is

begin

process(BCDin)
begin

case BCDin is
when "0000" =>
Seven_Segment <= "0000001"; ---0
when "0001" =>
Seven_Segment <= "1001111"; ---1
when "0010" =>
Seven_Segment <= "0010010"; ---2
when "0011" =>
Seven_Segment <= "0000110"; ---3
when "0100" =>
Seven_Segment <= "1001100"; ---4
when "0101" =>
Seven_Segment <= "0100100"; ---5
when "0110" =>
Seven_Segment <= "0100000"; ---6
when "0111" =>
Seven_Segment <= "0001111"; ---7
when "1000" =>
Seven_Segment <= "0000000"; ---8
when "1001" =>
Seven_Segment <= "0000100"; ---9
when others =>
Seven_Segment <= "1111111"; ---null
end case;

end process;

end Behavioral;

VHDL Testbench Code for BCD to 7 segment display
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_bcd_7seg IS
END tb_bcd_7seg;

ARCHITECTURE behavior OF tb_bcd_7seg IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bcd_7segment
PORT(
BCDin : IN std_logic_vector(3 downto 0);
Seven_Segment : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;

--Inputs
signal BCDin : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal Seven_Segment : std_logic_vector(6 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: bcd_7segment PORT MAP (
BCDin => BCDin,
Seven_Segment => Seven_Segment
);

-- Stimulus process
stim_proc: process
begin

BCDin <= "0000";
wait for 100 ns;
BCDin <= "0001";
wait for 100 ns;
BCDin <= "0010";
wait for 100 ns;
BCDin <= "0011";
wait for 100 ns;
BCDin <= "0100";
wait for 100 ns;
BCDin <= "0101";
wait for 100 ns;
BCDin <= "0110";
wait for 100 ns;
BCDin <= "0111";
wait for 100 ns;
BCDin <= "1000";
wait for 100 ns;
BCDin <= "1001";
wait for 100 ns;
end process;

END;