Question

Write a Behavioral model VHDL code that implements an ALU that can perform addition, subtraction, multiplication, shift right, shift left, logical NAND, and logical NOR. Write a VHDL test bench to test the ALU with at least one test vector per operation.

Answer 1

-----------------------------------------
-- OpCode Output (Y)
------------------------------------------
-- 000 A + B
-- 001 A - B
-- 010 B - A
-- 011 A * B
-- 100 A shift right by 1 bit
-- 101 A shift left by 1 bit
-- 110 A logical NAND with B
-- 111 A logical NOR with B
------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- assume A and B are of 4 bits, and output Y are of 8 bits
-- sel is the selection bit between different operation

entity alu_design is
port (
  A : in std_logic_vector ( 3 downto 0 );
  B : in std_logic_vector ( 3 downto 0 );
  OpCode : in std_logic_vector ( 2 downto 0 );
  Y : out std_logic_vector ( 7 downto 0 )
);
end alu_design;

architecture behavioral of alu_design is
signal tempA, tempB : std_logic_vector(7 downto 0);
  begin
   -- To make it compile clean
   tempA <= '0' & '0' & '0' & '0' & A(3 downto 0);
   tempB <= '0' & '0' & '0' & '0' & B(3 downto 0);

   process(tempA, tempB, OpCode)
   begin
   case OpCode is
   when "000" => Y <= tempA + tempB;
   when "001" => Y <= tempA - tempB;
   when "010" => Y <= tempB - tempA;
   when "011" => Y <= tempA(3 downto 0) * tempB(3 downto 0);
   when "100" => Y <= '0' & tempA(7 downto 1);
   when "101" => Y <= tempA(6 downto 0) & '0';
   when "110" => Y <= tempA nand tempB;
   when "111" => Y <= tempA nor tempB;
   when others => Y <= A;
   end case;
   end process;

end behavioral;



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity alu_design_tb is
end alu_design_tb;

architecture testbench of alu_design_tb is
component alu_design
port (
  A : in std_logic_vector ( 3 downto 0 );
  B : in std_logic_vector ( 3 downto 0 );
  OpCode : in std_logic_vector ( 2 downto 0 );
  Y : out std_logic_vector ( 7 downto 0 )
);
end component;

signal A, B : std_logic_vector(7 downto 0);
signal OpCode : std_logic_vector(2 downto 0);
signal Y : std_logic_vector(7 downto 0);

begin


dut : alu_design port map (A => A, B => B, OpCode => OpCode, Y => Y);

process
  begin
   A <= "1100";
   B <= "0111";
   OpCode <= "000";
   wait for 10 ns;

   OpCode <= "001";
   wait for 10 ns;

   OpCode <= "010";
   wait for 10 ns;

   OpCode <= "011";
   wait for 10 ns;

   OpCode <= "100";
   wait for 10 ns;

   OpCode <= "101";
   wait for 10 ns;

   OpCode <= "110";
   wait for 10 ns;

   OpCode <= "111";
   wait for 10 ns;
   wait;

end process;

end testbench;