Question

In: Computer Science

5. On a machine, an instruction is always 16 bits long, and there are 16 registers....

5. On a machine, an instruction is always 16 bits long, and there are 16 registers. There are only two types of instruction supported:

  • dyadic operation, which has 2 operands, and
  • monadic operations, which has only 1 operand.

If we want to make sure the machine can support 64 different monadic instructions, then how many dyadic instructions can it support at most? (10%)

--------------------------------

6. Let us assume we have such a machine. The physical RAM has 32 bytes, and is evenly divided into 4 pages. The virtual memory has 16 pages.

Physical RAM

Page Num

Page

data

3

11

~QWERTYU

2

10

IOPASDFG

1

01

HJKLZXCV

0

00

BNM<>[]?

Page table

15

0

14

0

13

0

12

1

01

11

0

10

0

9

1

11

8

0

7

0

6

0

5

1

00

4

0

3

1

10

2

0

1

0

0

0

The content in the page table and physical RAM is shown below:

Let us assume in a page, the offset of the left most byte is 0, and the offset of the right most byte is 7. If we are going to access the following virtual memory addresses, what is the data we will see? (10%)

0101 001

0011 000

1100 110

1001 011

--------------------------------

7.

  1. Assume that the cache size is 512kB, and each cache line is 128 Bytes.
  1. If it’s a 4-way associative cache, how many sets are there? If it’s a 2-way associative cache, how many sets are there? (5%)

  1. Let’s assume the cache is initially empty, and LRU policy is used for cache line replacement. If the following memory blocks are accessed:

Mem-block # 7, 1031, 2055, 4103, 1031, 7, 2055, 3079, 1031, 3079

What is the cache hit/miss rate if the cache is 4-way associative? Put “Hit” or “Miss” in the blanks in the table below. (5%)

7

1031

2055

4103

1031

7

2055

3079

1031

3079

  1. Given the same conditions as the question above, what is the cache hit/miss rate if the cache is 2-way associative? Put “Hit” or “Miss” in the blanks in the table below. (5%)

7

1031

2055

4103

1031

7

2055

3079

1031

3079

Solutions

Expert Solution

As per the guidelines, among multiple questions the first needs to be answered.

Therefore, the answer of the first question 5 is provided below:

5.

Solution:


Related Solutions

In a computer instruction format, the instruction length is 11 bits and the size of an...
In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have 5 two-address instructions 45 one-address instructions 32 zero-address instructions using the specified format? Justify your answer.
In a computer instruction format, the instruction length is 12 bits and the size of an...
In a computer instruction format, the instruction length is 12 bits and the size of an address field is 5 bits. The system architect has already designed three 2-address instructions and thirty one 1-address instructions. How many 0-address instructions can still be possibly accommodated?
Example: A 3-address computer has 40 instructions, 16 Registers, and 256KB memory. Assume each instruction has...
Example: A 3-address computer has 40 instructions, 16 Registers, and 256KB memory. Assume each instruction has three operands. Two registers and the third operand is a direct address location of a memory. Find minimum size of PC, MAR, MDR, IR. Solution: OPCODE R1, R2, address OPCODE is 6 bits since 2^6>40 Register field is 4 bits since 2^4 =16 Memory field is 18 bits since 2^18=256K Instruction length =6+4+4+18=32 bits MDR=32 bits IR=32 bits MAR=18 PC=18 Please explain
Latches are commonly organized into groups of 4-bits, 8-bits or more into registers. 1 point True...
Latches are commonly organized into groups of 4-bits, 8-bits or more into registers. 1 point True False An asynchronous counter is one where all stages of the counter trigger together. 1 point True False Pull-up resistors and special interface ICs are typically used as an interface between different logic families. 1 point True False Which logic gate provides a low output only when an odd number of inputs are high? 1 point and or exclusive OR exclusive NOR Which of...
13. A digital computer has a memory unit with 32 bits per word. The instruction set...
13. A digital computer has a memory unit with 32 bits per word. The instruction set consists of 260 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory? d) What...
Write instruction(s) in C to get bits 4 and 7 of Port-C, then compute the “XOR...
Write instruction(s) in C to get bits 4 and 7 of Port-C, then compute the “XOR (exclusive OR)” of these two bits and write the result of the “XOR operation” to bit 4 of Port-D.
Write instruction(s) in C to get bits 4 and 7 of Port-C, then compute the “XOR...
Write instruction(s) in C to get bits 4 and 7 of Port-C, then compute the “XOR (exclusive OR)” of these two bits and write the result of the “XOR operation” to bit 4 of Port-D.
A digital computer has a memory unit with 32 bits per word. The instruction set consists...
A digital computer has a memory unit with 32 bits per word. The instruction set consists of 122 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory? d) What is...
1. Assume we have 8 registers, R0~R7, and we have a pipeline of 6 stages: Instruction...
1. Assume we have 8 registers, R0~R7, and we have a pipeline of 6 stages: Instruction Fetch (IF), Instruction Issue (II), Operands Fetch (OF), Execution (EX), Write Back (WB), and Commitment (CO). Each stage needs exactly 1 cycle to finish its work. Also assume that the pipeline supports forwarding, which means the result of WB can be forwarded to OF. Given the following piece of instructions: R1 = R0 + R2 R3 = R4 + R5 R6 = R1 +...
True and False 1. The instruction register stores machine code for the instruction being executed. 2....
True and False 1. The instruction register stores machine code for the instruction being executed. 2. Before a digital computer may execute an instruction, the instruction code must be fetched from memory. 3. A pointer is a binary code for data in the arithmetic logic unit. 4. Von Neumann computer architecture stores data and instruction codes in the same memory. 5. Complex instruction set computers have instructions with greater speed than those in reduced instruction set computers.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT