Question

In: Computer Science

Answer the following questions about cache coherency protocols in a dual-processor system. a) If each processor...

Answer the following questions about cache coherency protocols in a dual-processor system.

a) If each processor has a separate cache, what is the main advantage of the 4-state MESI snoopy cache coherency protocol compared to a snoopy cache coherency protocol that uses only 3 states M, S and I (modified, shared and invalid)?

b) Suppose that processor P1 (in a dual-processor system) writes to a memory block. A copy of this same memory block is already in a modified line within the local cache of processor P2. What action should be taken for the modified line within P2’s cache? Explain your answer.

c) Assume that the 3-state MSI cache coherency protocol is used with a single 2-way set associative cache containing a total of 1048576 lines each of which is 512 bytes in size. What is the minimum total number of MSI state bits needed for the entire cache?

Solutions

Expert Solution

a)

MSI refers to Modified Shared Invalid whereas MESI refers to Modified Exclusive Shared Invalid. The difference between the two protocols is that MESI protocol adds an exclusive state. The exclusive helps in saving a useless bus request.

Suppose processor 'A' has a block that is to be read & then written to and no other processor has the said block. According to MSI protocol, two bus transaction will be made by processor 'A':

1. Request to read the block.

2. Request to write to the said block.

The second request is pointless because only processor A's cache has the said block and no request needs to be made to write to other processor's caches as they don't have it.

This is where MESI protocol comes in, it overcomes this situation by adding an exclusive state and prevents the second bus transaction from being made. Processor 'A' will follow MESI protocol and it will enter exclusive state because it is the only processor said block and as the only working processor on the said task, it will have exclusive access and won't need to make second bus transaction.

b)

No action should be taken for the modified line within P2’s cache and it should remain the Modified state as it needs to be written back to the memory block and it is only possible in either Modified or Exclusive state and Exclusive state isn't possible as the processor P1 has it as well. After the write back, the line is change to Shared state. Therefore:

-State remains same i.e. Modified. and,

-is written to the memory block in future.

c)

Total no. of lines = 1048576

Size of 1 line = 512 bytes


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