In: Computer Science
For first level cache:
The main reason for first level split cache(L1) in instruction and data cache is to increase the bandwidth. By using split cache, the data and the instructions can be read simultaneously by the processor and thus reducing time. Also, it helps to avoid structural hazard i.e. in case of overlapping instructions in pipelining, both the resources(instruction and data cache) can be used simultaneously. Another reason is that there is different type of data in instruction cache and data cache and therefore, can simplify the circuitry.
For second level cache:
The second level cache is unified because, it requires replication or multi-porting or multi-banking and if limited bandwidth is supplied, it can slow down the hit time. The L2 cache is accessed less frequently so there are lesser chances of structural hazards but to reduce the miss rate, the instruction and data cache are combined in a single cache because lowering the miss rate avoid accessed to the main memory.