Suppose some FSM has 3 inputs, internal Ready, external
bus-grant Grant, and external bus-free Free signals, as well as 2
outputs, bus-request Req and bus-lock Lock signals. Show its
Moore-type state diagram, assuming that the FSM implements the
following bus protocol: (1) initially, the FSM outputs Req = 0 and
Lock = 0 and waits for both Ready and Free to be asserted; (2)
After receiving Ready = 1 and Free = 1, the FSM outputs Req = 1 and...