Design a 5-bit binary counter using JK flip flops.
Draw the flip-flop circuit diagram, the state graph, the timing
diagram, the truth table (with clk pulse) and the state table (with
present and next states).
Implement the synchronous 2-bit Up/Down counter with saturation
at the end states. The flip-flop outputs Q1, Q0 serve as the
outputs of the counter. The counting direction is set with mode
control input M. With M =1 the flip-flop outputs follow the
incrementing binary sequence starting from a current state with
saturation at state 11 as shown in the following example: 00->
01-> 10-> 11-> 11-> 11... With M =0 the outputs follow
the decrementing binary sequence from a current...
Implement the synchronous 2-bit Up/Down counter with
saturation at the end states. The flip-flop outputs Q1, Q0 serve as
the outputs of the counter.
The counting direction is set with mode control input M.
With M =1 the flip-flop outputs follow the incrementing binary
sequence starting from a current state with saturation at state 11
as shown in the following example: 00-> 01-> 10-> 11->
11-> 11...
With M =0 the outputs follow the decrementing binary sequence
from a current state...
Use JK-Flip-Flop to design a sequential circuit as an input for
the previous designed decoder to write UAE. In
this design, the sequential circuit will be used instead of the two
bits switches and the output will be shown in three 7-segment
displays one for each letter. Letters must glow one by one in a
correct sequence where the speed depends on the clock
frequency.
Use only one circuit as an input for the three 7-segment
displays where one of...
Flip-flops:
a) Make a asyncronous MOD 12 flip-flop up counter circuit
b) Make a syncronous MOD 14 flip-flop up counter circuit
c) Each flip-flop has the same propagation delay, which is 10ms.
Calculate the maximum clock frequency of the circuit in questions
(a) and (b)
You are to implement the following in VHDL:
D flip-flop
D flip-flop with enable
and reset
J-K flip flop with asynchronous set
T Flip flop with asynchronous clear
(a) Design a 4-bit ring counter. Use an external asynchronous
INIT input to initialize the flip-flops to a valid initial state.
Also remember to hook up the CLOCK to all flip-flops.
(b) Design a 4-bit Johnson counter. Use an external asynchronous
INIT input to initialize the flip-flops to a valid initial state.
Also remember to hook up the CLOCK to all flip-flops.
(c) How many states does the ring counter in part (a) have? How
many states does the Johnson...