In: Electrical Engineering
Your cache has a hit time of 1 clock cycle and a miss time of 100 clock cycles. If the CPI of your processor equals 1.3 with perfect caches (the cache always hits), then what is the CPI if your cache hits 71% of the time? Fill in the blank and show your work.
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Your cache has a miss penalty of 50 clock cycles and a hit time of 1 clock cycle. If your processor has a CPI of 1.5 with a perfect cache (it always hits), then what is your CPI if your cache always misses? one of them is correct.
a. 1.5 |
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b. 50.5 |
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c. 51.5 |
Multiple-level caches are used because they?
a. provide a balance between low hit time and low miss rate.
b. have a higher combined hit rate than a single-level cache of the same size.
c. remove the need for a secondary memory.
Answer for next subquestion:
References :
http://home.ku.edu.tr/comp303/public_html/Lecture15.pdf
https://www.cs.umb.edu/cs641/notes10.html
https://courses.cs.washington.edu/courses/cse378/09wi/lectures/lec18.pdf