When is an external interrupt recognized by the
CPU? When more than one interrupt occurs, what
approaches would you use to service them? What approaches should be
taken when an interrupt occurs within an interrupt service
routine
Consider a hypothetical microprocessor having 64-bit
instructions composed of two fields: the first 16-bits contains the
op-code and the remainder the immediate operand or an operand
address. Assume memory is organized in 32-bit words,
i.e. one r/w access can yield a maximum of 32
bits. ...