Question

In an asynchronous bus, what are the steps that a master device let a slave device do a job?

Please draw the circuit diagram of an SR latch using only NAND gates. Please also show its truth.

Answer 1

Asynchronous Buses-A bus in which the pace of the bus protocol is NOT steered by a clock signal is known as asynchronous bus.In bus protocol devices which are connected to bus know other devices state when they take next step.
There will be two control signals that is used for designing of asynchronous communication protocol. These signals are

MSYNC- Master Sync signal- This signal is used for master device that master device is ready for communication protocol.

SSYNC- Slave Sync signal-This signal is used for slave device that slave device is ready for communication protocol.

Those devices which initiate communication are called master devices and those devices who want to communicate is known as slave devices.For instance in computer CPU is master device because in read operation CPU request to memory for data whereas memory is slave device.
There are following steps when CPU reads data from memory using an asynchronous bus.
1) CPU (master device ) sends out address value, claim MREQ i.e a request to made memory and READ means
an address value will be provided to memory.
2) CPU(Master device) claims MSYNC i.e.CPU is ready
3) CPU(Master device) waits for slave(memory) it send signal that data is ready
4) When SSYNC is claimed at that time CPU copies data into MBR.
5) CPU detach MSYNC
6) CPU detach the address and the memory read request

SR latch using only NAND gates-