Question

i have to be able to teach and explain by presentation " designing a synchronous counter in VHDL" thank you, please layman terms

Answer 1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity down_count is

    Port ( clk,rst : in  STD_LOGIC;

           count : out  STD_LOGIC_VECTOR (3 downto 0));

end down_count;

architecture Behavioral of up_count is

signal temp:std_logic_vector(3 downto 0);

begin

process(clk,rst)

begin

if(rst='1')then

temp<="1111";

elsif(rising_edge(clk))then

temp<=temp-1;

end if;

end process;

count<=temp;

end Behavioral;

3-bit synchronous up-down counter. Notice the multiplexers.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown_count is

    Port ( clk,rst,updown : in  STD_LOGIC;

           count : out  STD_LOGIC_VECTOR (3 downto 0));

end updown_count;

architecture Behavioral of up_count is

signal temp:std_logic_vector(3 downto 0);

begin

process(clk,rst)

begin

if(rst='1')then

temp<="0000";

elsif(rising_edge(clk))then

if(updown='1')then

temp<=temp+1;

else

temp<=temp-1;

end if;

end if;

end process;

count<=temp;

end Behavioral;