Question

(i) Consider a CMOS inverter supplied at V_DD= 5V with transistor parameters of K_N=K_P=50µA/V² and V_TN=-V_TP=1V. Then consider another CMOS inverter supplied at V_DD= 10V with the same transistor parameters. Draw the VTC of both inverters showing all regions of operation and the middle voltage VM. Verify your results using PSpice.

            (ii) Draw the square root of the CMOS inverter current versus the input voltage for the two CMOS inverters in given in part (i) biased at either V_DD=5 V or V_DD=10 V. Determine the peak current of the CMOS inverter at V_DD=5 V & V_DD=10 V. Verify your results using PSpice.

(iii) Consider NMOS inverter supplied at V_DD= 5V with transistor parameters of K_Driver=10 K_Load=100µA/V² and V_T =0.7V. Calculate the power dissipated for the following input conditions: Vin= 0.25 V and Vin=4.3 V.

(iv) If two NOR gates based on the CMOS inverter given in part (i) which supplied at V_DD= 5V are connected to realize an SR Flip Flop. Sketch the NOR gate and sketch the complete circuit of the SR Flip Flop indicating the S and R inputs a well as the Q output. What are the logic”0” and logic “1” levels of this Flip Flop?

(v) If two NOR gates based on the NMOS inverter given in part (iii) are connected to realize an SR Flip Flop. Sketch the NOR gate and sketch the complete circuit of the SR Flip Flop indicating the S and R inputs a well as the Q output. What are the logic”0” and logic “1” levels of this Flip Flop?

Answer 1