Question

1.What is a “structural hazard?” What structural hazards does the MIPS R5000 processor, under discussion, have?
2.   Describe the stages of the MIPS R5000 processor

3.Describe the differences between forwarding and stalling
4.Why is pipelining dependent on technology

9.   Describe the choices for multiple instruction issue.

8.   What are “control hazards?” Describe the mechanism presented to avoid them.

Answer 1

1.Structural hazards are due to limited hardware resources or when the multiple instructions try to access the same set of resources causing conflict issues. Resources that are affected are register and file memory.

The Structural hazard under the MIPS-5000 can occur when the one instruction is present in the ID stage which requires register file read access, while the other one is present in the WB stage which requires register file write access. If the register file has only one port then the hazard can occur.

2.The Stages that occur under the MIPS-5000 Processor are

a.) Instruction fetch stage - Fetches the next instruction from the memory using the address in the program counter register and stores the instruction in the instruction register.

b.)The Instruction Decode stage decodes the instruction in the instruction register, calculates the next program counter, and reads the operands from the register file.

c.)The Execute stage "executes" all the instructions, and all ALU operations are done under this stage.

d.)The Memory Access stage, for loads, it would load an operand from memory. For stores, it would store an operand into memory. For all other instructions, it would do nothing.

3.) Forwarding is used to eliminate the data hazards but it doesn't mean it always eliminates the data hazard whereas stalling is a guaranteed solution for eliminating the data hazard.

4.) pipelining is dependent on technology because it is used to prevent the super-lined processor from being slower to the superscalar and the technology used in this is GAAS which reduces the delay of the lengthy instruction pipeline.

9.) The choices for multiple instruction issue is instruction fetch that is implemented simultaneously on the multithreading processor

i) Minimize the architectural impact on the conventional superscalar design

ii) it has a minimal performance impact on a single thread executing alone

iii) it achieves significant throughput gains when running multiple threads.

8) Control hazards can occur when the decision before branch before condition calculation is done and this can be resolved by stalling the instruction following branch instruction until the condition is determined.

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