Question

1. A testbench is provided in the following directory (~lab_work/verification/task3) without the Device Under Test (DUT).(see testbench below)

`timescale 1ns/10ps

module tb_detector ;

reg clk, rst, datain;
wire det;

detector DUT ( .clk(clk), .rst(rst), .datain(datain), .det(det) );


initial
begin
#0 clk = 0;
datain = 0;
forever #5 clk = ~clk;
end

initial
begin
#0 rst = 0;
@ (negedge clk);
@ (negedge clk);
rst = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;

@(posedge clk)
#2 if (det == 0)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;

#100 $finish;
end



endmodule

2. Write a verilog code for the DUT that will do the following:

i) receive clk, rst dan datain signals from the provided testbench

ii) reset the output signal to LOW synchronously with the positive (rising) edge of clk when rst is set LOW

iii) produce an output signal similar to datain when rst is HIGH and the output transition occurs at the negative (falling) edge of clk.

3. Verify the design using the testbench.

Answer 1

Verylog Code for DUT:

​​​​​​module detector(clk,rst,datain,det); //initialise the module
input clk,rst,datain;//declare inputs
output reg det;//declare outputs
initial det=0 ;//give initial value for det
always@(posedge clk)//define always block
begin
if(rst==1'b0)// if rst is low then output is low
det<=1'b0;
end
always@(negedge clk) //define another always
begin
if(rst==1'b1) // if reset Is high output is datain
det<=datain;
end // end the always block
endmodule// end the module

Code:

output:

Console output:

please note that I have not uploaded the test bench since the same given test bench is used

please comment if you have any doubts...

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